\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Port T Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0 : PT0
bits : 0 - 0 (1 bit)
access : read-write
PT1 : PT1
bits : 1 - 1 (1 bit)
access : read-write
PT2 : PT2
bits : 2 - 2 (1 bit)
access : read-write
PT3 : PT3
bits : 3 - 3 (1 bit)
access : read-write
PT4 : PT4
bits : 4 - 4 (1 bit)
access : read-write
PT5 : PT5
bits : 5 - 5 (1 bit)
access : read-write
PT6 : PT6
bits : 6 - 6 (1 bit)
access : read-write
PT7 : PT7
bits : 7 - 7 (1 bit)
access : read-write
Port T Function Register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0F4 : PT0F4
bits : 0 - 0 (1 bit)
access : read-write
PT1F4 : PT1F4
bits : 1 - 1 (1 bit)
access : read-write
PT2F4 : PT2F4
bits : 2 - 2 (1 bit)
access : read-write
PT3F4 : PT3F4
bits : 3 - 3 (1 bit)
access : read-write
PT4F4 : PT4F4
bits : 4 - 4 (1 bit)
access : read-write
PT5F4 : PT5F4
bits : 5 - 5 (1 bit)
access : read-write
Port T Function Register 5
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0F5 : PT0F5
bits : 0 - 0 (1 bit)
access : read-write
PT1F5 : PT1F5
bits : 1 - 1 (1 bit)
access : read-write
PT2F5 : PT2F5
bits : 2 - 2 (1 bit)
access : read-write
Port T Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0OD : PT0OD
bits : 0 - 0 (1 bit)
access : read-write
PT1OD : PT1OD
bits : 1 - 1 (1 bit)
access : read-write
PT2OD : PT2OD
bits : 2 - 2 (1 bit)
access : read-write
PT3OD : PT3OD
bits : 3 - 3 (1 bit)
access : read-write
PT4OD : PT4OD
bits : 4 - 4 (1 bit)
access : read-write
PT5OD : PT5OD
bits : 5 - 5 (1 bit)
access : read-write
PT6OD : PT6OD
bits : 6 - 6 (1 bit)
access : read-write
PT7OD : PT7OD
bits : 7 - 7 (1 bit)
access : read-write
Port T Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0UP : PT0UP
bits : 0 - 0 (1 bit)
access : read-write
PT1UP : PT1UP
bits : 1 - 1 (1 bit)
access : read-write
PT2UP : PT2UP
bits : 2 - 2 (1 bit)
access : read-write
PT3UP : PT3UP
bits : 3 - 3 (1 bit)
access : read-write
PT4UP : PT4UP
bits : 4 - 4 (1 bit)
access : read-write
PT5UP : PT5UP
bits : 5 - 5 (1 bit)
access : read-write
PT6UP : PT6UP
bits : 6 - 6 (1 bit)
access : read-write
PT7UP : PT7UP
bits : 7 - 7 (1 bit)
access : read-write
Port T Pull-down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0DN : PT0DN
bits : 0 - 0 (1 bit)
access : read-write
PT1DN : PT1DN
bits : 1 - 1 (1 bit)
access : read-write
PT2DN : PT2DN
bits : 2 - 2 (1 bit)
access : read-write
PT3DN : PT3DN
bits : 3 - 3 (1 bit)
access : read-write
PT4DN : PT4DN
bits : 4 - 4 (1 bit)
access : read-write
PT5DN : PT5DN
bits : 5 - 5 (1 bit)
access : read-write
PT6DN : PT6DN
bits : 6 - 6 (1 bit)
access : read-write
PT7DN : PT7DN
bits : 7 - 7 (1 bit)
access : read-write
Port T Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0IE : PT0IE
bits : 0 - 0 (1 bit)
access : read-write
PT1IE : PT1IE
bits : 1 - 1 (1 bit)
access : read-write
PT2IE : PT2IE
bits : 2 - 2 (1 bit)
access : read-write
PT3IE : PT3IE
bits : 3 - 3 (1 bit)
access : read-write
PT4IE : PT4IE
bits : 4 - 4 (1 bit)
access : read-write
PT5IE : PT5IE
bits : 5 - 5 (1 bit)
access : read-write
PT6IE : PT6IE
bits : 6 - 6 (1 bit)
access : read-write
PT7IE : PT7IE
bits : 7 - 7 (1 bit)
access : read-write
Port T Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0C : PT0C
bits : 0 - 0 (1 bit)
access : read-write
PT1C : PT1C
bits : 1 - 1 (1 bit)
access : read-write
PT2C : PT2C
bits : 2 - 2 (1 bit)
access : read-write
PT3C : PT3C
bits : 3 - 3 (1 bit)
access : read-write
PT4C : PT4C
bits : 4 - 4 (1 bit)
access : read-write
PT5C : PT5C
bits : 5 - 5 (1 bit)
access : read-write
PT6C : PT6C
bits : 6 - 6 (1 bit)
access : read-write
PT7C : PT7C
bits : 7 - 7 (1 bit)
access : read-write
Port T Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT6F1 : PT6F1
bits : 6 - 6 (1 bit)
access : read-write
PT7F1 : PT7F1
bits : 7 - 7 (1 bit)
access : read-write
Port T Function Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT0F2 : PT0F2
bits : 0 - 0 (1 bit)
access : read-write
PT1F2 : PT1F2
bits : 1 - 1 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.