\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xDC Bytes (0x0)
size : 0x9C byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x178 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x19C Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x1BC Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected
VE enable_disable
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VEEN : VEEN
bits : 0 - 0 (1 bit)
access : read-write
Schedule repeat count
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREP : VREP
bits : 0 - 3 (4 bit)
access : read-write
Start trigger mode
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRG : VTRG
bits : 0 - 1 (2 bit)
access : read-write
ADC start wait setting
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TADC : TADC
bits : 0 - 15 (16 bit)
access : read-write
PMD control_ CMPU setting
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCMPU : VCMPU
bits : 0 - 15 (16 bit)
access : read-write
Error interrupt enable_disable
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VERREN : VERREN
bits : 0 - 0 (1 bit)
access : read-write
INTTEN : INTTEN
bits : 2 - 2 (1 bit)
access : read-write
PMD control_ CMPV setting
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCMPV : VCMPV
bits : 0 - 15 (16 bit)
access : read-write
PMD control_ CMPW setting
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCMPW : VCMPW
bits : 0 - 15 (16 bit)
access : read-write
PMD control_ Output control (MDOUT)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UOC : UOC
bits : 0 - 1 (2 bit)
access : read-write
VOC : VOC
bits : 2 - 3 (2 bit)
access : read-write
WOC : WOC
bits : 4 - 5 (2 bit)
access : read-write
UPWM : UPWM
bits : 6 - 6 (1 bit)
access : read-write
VPWM : VPWM
bits : 7 - 7 (1 bit)
access : read-write
WPWM : WPWM
bits : 8 - 8 (1 bit)
access : read-write
PMD control_ TRGCMP0 setting
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRGCMP0 : VTRGCMP0
bits : 0 - 15 (16 bit)
access : read-write
PMD control_ TRGCMP1 setting
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRGCMP1 : VTRGCMP1
bits : 0 - 15 (16 bit)
access : read-write
PMD control_ Trigger selection
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRGSEL : VTRGSEL
bits : 0 - 2 (3 bit)
access : read-write
PMD control_ EMG return (EMGCR_EMGRS_)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EMGRS : EMGRS
bits : 0 - 0 (1 bit)
access : write-only
PI controled output limit value setting
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIOLIM : PIOLIM
bits : 0 - 15 (16 bit)
access : read-write
VE forced termination
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VCEND : VCEND
bits : 0 - 0 (1 bit)
access : write-only
PI controled d-axis coefficient range setting
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIDKIG : CIDKIG
bits : 0 - 7 (8 bit)
access : read-write
CIDKPG : CIDKPG
bits : 8 - 15 (8 bit)
access : read-write
PI controled q-axis coefficient range setting
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIQKIG : CIQKIG
bits : 0 - 7 (8 bit)
access : read-write
CIQKPG : CIQKPG
bits : 8 - 15 (8 bit)
access : read-write
Voltage scalar limits
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSLIM : VSLIM
bits : 0 - 15 (16 bit)
access : read-write
Voltage scalar
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDQ : VDQ
bits : 0 - 15 (16 bit)
access : read-write
Declination angle
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELTA : DELTA
bits : 0 - 15 (16 bit)
access : read-write
Motor interlinkage magnetic flux
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHI : CPHI
bits : 0 - 15 (16 bit)
access : read-write
Motor q-axis inductance
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLD : CLD
bits : 0 - 15 (16 bit)
access : read-write
Motor d-axis inductance
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLQ : CLQ
bits : 0 - 15 (16 bit)
access : read-write
Motor resistance value
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR : CR
bits : 0 - 15 (16 bit)
access : read-write
Motor magnetic flux range setting
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHIG : CPHIG
bits : 0 - 2 (3 bit)
access : read-write
Motor inductance range setting
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLG : CLG
bits : 0 - 2 (3 bit)
access : read-write
Motor resistance range setting
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRG : CRG
bits : 0 - 2 (3 bit)
access : read-write
Non-interference controled d-axis voltage
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDE : VDE
bits : 0 - 15 (16 bit)
access : read-write
Non-interference controled q-axis voltage
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VQE : VQE
bits : 0 - 15 (16 bit)
access : read-write
Dead time compensation
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTC : DTC
bits : 0 - 15 (16 bit)
access : read-write
Hysteresis width for current discrimination
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : HYS
bits : 0 - 15 (16 bit)
access : read-write
Error detection
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERRD : VERRD
bits : 0 - 0 (1 bit)
access : read-only
Dead time compensation control _ status
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IASTS : IASTS
bits : 0 - 2 (3 bit)
access : read-write
IBSTS : IBSTS
bits : 4 - 6 (3 bit)
access : read-write
ICSTS : ICSTS
bits : 8 - 10 (3 bit)
access : read-write
PWM upper limit setting
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMMAX : PWMMAX
bits : 0 - 15 (16 bit)
access : read-write
PWM lower limit setting
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMMIN : PWMMIN
bits : 0 - 15 (16 bit)
access : read-write
Clipped phase value setting
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THTCLP : THTCLP
bits : 0 - 15 (16 bit)
access : read-write
The second threshold value for determining the current polarity
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS2 : HYS2
bits : 0 - 15 (16 bit)
access : read-write
ALPHA-phase voltage
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALPHA : VALPHA
bits : 0 - 31 (32 bit)
access : read-write
BETA-phase voltage
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBETA : VBETA
bits : 0 - 31 (32 bit)
access : read-write
A-phase duty
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDUTYA : VDUTYA
bits : 0 - 31 (32 bit)
access : read-write
B-phase duty
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDUTYB : VDUTYB
bits : 0 - 31 (32 bit)
access : read-write
C-phase duty
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDUTYC : VDUTYC
bits : 0 - 31 (32 bit)
access : read-write
ALPHA-phase current
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IALPHA : IALPHA
bits : 0 - 31 (32 bit)
access : read-write
BETA-phase current
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBETA : IBETA
bits : 0 - 31 (32 bit)
access : read-write
A-phase current
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IA : IA
bits : 0 - 31 (32 bit)
access : read-write
B-phase current
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IB : IB
bits : 0 - 31 (32 bit)
access : read-write
C-phase current
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC : IC
bits : 0 - 31 (32 bit)
access : read-write
VDQ Declination angle
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDELTA : VDELTA
bits : 0 - 15 (16 bit)
access : read-write
Schedule executing flag_executing task
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VRSCH : VRSCH
bits : 0 - 0 (1 bit)
access : read-only
VRTASK : VRTASK
bits : 1 - 4 (4 bit)
access : read-only
d-axis voltage correction value
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDCRC : VDCRC
bits : 0 - 15 (16 bit)
access : read-write
q-axis voltage correction value
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VQCRC : VQCRC
bits : 0 - 15 (16 bit)
access : read-write
Temporary register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPREG0 : TMPREG0
bits : 0 - 31 (32 bit)
access : read-write
Temporary register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPREG1 : TMPREG1
bits : 0 - 31 (32 bit)
access : read-write
Temporary register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPREG2 : TMPREG2
bits : 0 - 31 (32 bit)
access : read-write
Temporary register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPREG3 : TMPREG3
bits : 0 - 31 (32 bit)
access : read-write
Temporary register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPREG4 : TMPREG4
bits : 0 - 31 (32 bit)
access : read-write
CPU start trigger selection
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VCPURT : VCPURT
bits : 0 - 0 (1 bit)
access : write-only
Temporary register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPREG5 : TMPREG5
bits : 0 - 31 (32 bit)
access : read-write
Status flags
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAVF : LAVF
bits : 0 - 0 (1 bit)
access : read-write
LAVFM : LAVFM
bits : 1 - 1 (1 bit)
access : read-write
LVTF : LVTF
bits : 2 - 2 (1 bit)
access : read-write
PLSLF : PLSLF
bits : 4 - 4 (1 bit)
access : read-write
PLSLFM : PLSLFM
bits : 5 - 5 (1 bit)
access : read-write
PIDOVF : PIDOVF
bits : 8 - 8 (1 bit)
access : read-write
PIQOVF : PIQOVF
bits : 9 - 9 (1 bit)
access : read-write
VSOVF : VSOVF
bits : 10 - 10 (1 bit)
access : read-write
PWMOVF : PWMOVF
bits : 11 - 11 (1 bit)
access : read-write
SFT2ST : SFT2ST
bits : 14 - 14 (1 bit)
access : read-write
SFT2STM : SFT2STM
bits : 15 - 15 (1 bit)
access : read-write
Task control mode
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVIEN : PVIEN
bits : 0 - 0 (1 bit)
access : read-write
ZIEN : ZIEN
bits : 1 - 1 (1 bit)
access : read-write
OCRMD : OCRMD
bits : 2 - 3 (2 bit)
access : read-write
VDCSEL : VDCSEL
bits : 4 - 4 (1 bit)
access : read-write
ATANMD : ATANMD
bits : 5 - 6 (2 bit)
access : read-write
CLPEN : CLPEN
bits : 7 - 7 (1 bit)
access : read-write
AWUMD : AWUMD
bits : 8 - 9 (2 bit)
access : read-write
T5ECEN : T5ECEN
bits : 10 - 10 (1 bit)
access : read-write
NICEN : NICEN
bits : 11 - 11 (1 bit)
access : read-write
PWMBLEN : PWMBLEN
bits : 12 - 12 (1 bit)
access : read-write
PWMFLEN : PWMFLEN
bits : 13 - 13 (1 bit)
access : read-write
PMDDTCEN : PMDDTCEN
bits : 14 - 14 (1 bit)
access : read-write
IPDEN : IPDEN
bits : 15 - 15 (1 bit)
access : read-write
Flow control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C2PEN : C2PEN
bits : 0 - 0 (1 bit)
access : read-write
SPWMEN : SPWMEN
bits : 1 - 1 (1 bit)
access : read-write
IDMODE : IDMODE
bits : 2 - 3 (2 bit)
access : read-write
IDQSEL : IDQSEL
bits : 4 - 4 (1 bit)
access : read-write
IAPLMD : IAPLMD
bits : 5 - 5 (1 bit)
access : read-write
IBPLMD : IBPLMD
bits : 6 - 6 (1 bit)
access : read-write
ICPLMD : ICPLMD
bits : 7 - 7 (1 bit)
access : read-write
CRCEN : CRCEN
bits : 8 - 8 (1 bit)
access : read-write
MREGDIS : MREGDIS
bits : 9 - 9 (1 bit)
access : read-write
VSLIMMD : VSLIMMD
bits : 10 - 11 (2 bit)
access : read-write
PHCVDIS : PHCVDIS
bits : 12 - 12 (1 bit)
access : read-write
CCVMD : CCVMD
bits : 13 - 13 (1 bit)
access : read-write
SPWMMD : SPWMMD
bits : 14 - 15 (2 bit)
access : read-write
PWM period rate (PWM period _s_ * maximum speed * 2^16) setting
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPWM : TPWM
bits : 0 - 15 (16 bit)
access : read-write
Rotation speed (speed _Hz_ _ maximum speed * 2^15) setting
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OMEGA : OMEGA
bits : 0 - 15 (16 bit)
access : read-write
Motor phase (motor phase _deg_ _ 360 * 2^16) setting
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THETA : THETA
bits : 0 - 15 (16 bit)
access : read-write
d-axis reference value (current _A_ _ maximum current * 2^15)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDREF : IDREF
bits : 0 - 15 (16 bit)
access : read-write
q-axis reference value (current _A_ _ maximum current * 2^15)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQREF : IQREF
bits : 0 - 15 (16 bit)
access : read-write
d-axis voltage (voltage _V_ _ maximum voltage * 2^31)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VD : VD
bits : 0 - 31 (32 bit)
access : read-write
q-axis voltage (voltage _V_ _ maximum voltage * 2^31)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VQ : VQ
bits : 0 - 31 (32 bit)
access : read-write
Integral coefficient for PI control of d-axis
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIDKI : CIDKI
bits : 0 - 15 (16 bit)
access : read-write
Proportional coefficient for PI control of d-axis
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIDKP : CIDKP
bits : 0 - 15 (16 bit)
access : read-write
Integral coefficient for PI control of q-axis
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIQKI : CIQKI
bits : 0 - 15 (16 bit)
access : read-write
Proportional coefficient for PI control of q-axis
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIQKP : CIQKP
bits : 0 - 15 (16 bit)
access : read-write
Upper 32 bits of integral term (VDI ) of d-axis voltage
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDIH : VDIH
bits : 0 - 31 (32 bit)
access : read-write
Task selection
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTASK : VTASK
bits : 0 - 3 (4 bit)
access : read-write
VITASK : VITASK
bits : 8 - 11 (4 bit)
access : read-write
Lower 32 bits of integral term (VDI) of d-axis voltage
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDILH : VDILH
bits : 16 - 31 (16 bit)
access : read-write
Upper 32 bits of integral term (VQI) of q-axis voltage
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VQIH : VQIH
bits : 0 - 31 (32 bit)
access : read-write
Lower 32 bits of integral term (VQI) of q-axis voltage
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VQILH : VQILH
bits : 16 - 31 (16 bit)
access : read-write
Switching speed (for 2-phase modulation and shift PWM)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPWMCHG : FPWMCHG
bits : 0 - 15 (16 bit)
access : read-write
SHIFT2 PWM Offset register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMOFS : PWMOFS
bits : 0 - 15 (16 bit)
access : read-write
Minimum pulse width
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MINPLS : MINPLS
bits : 0 - 15 (16 bit)
access : read-write
Synchronizing trigger correction value
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGCRC : TRGCRC
bits : 0 - 15 (16 bit)
access : read-write
Cosine value at THETA for output conversion (Q15 data)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDCL : VDCL
bits : 0 - 15 (16 bit)
access : read-write
Cosine value at THETA for output conversion (Q15 data)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COS : COS
bits : 0 - 15 (16 bit)
access : read-write
Sine value at THETA for output conversion (Q15 data)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIN : SIN
bits : 0 - 15 (16 bit)
access : read-write
Previous cosine value for input processing (Q15 data)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSM : COSM
bits : 0 - 15 (16 bit)
access : read-write
Previous sine value for input processing (Q15 data)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINM : SINM
bits : 0 - 15 (16 bit)
access : read-write
Sector information (0-11)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECTOR : SECTOR
bits : 0 - 3 (4 bit)
access : read-write
Previous sector information for input processing (0-11)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECTORM : SECTORM
bits : 0 - 3 (4 bit)
access : read-write
AD conversion result of a-phase zero-current
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IAO : IAO
bits : 0 - 15 (16 bit)
access : read-write
AD conversion result of b-phase zero-current
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBO : IBO
bits : 0 - 15 (16 bit)
access : read-write
Operation schedule selection
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VACT : VACT
bits : 0 - 3 (4 bit)
access : read-write
AD conversion result of c-phase zero-current
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICO : ICO
bits : 0 - 15 (16 bit)
access : read-write
AD conversion result of a-phase current
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IAADC : IAADC
bits : 0 - 15 (16 bit)
access : read-write
AD conversion result of b-phase current
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBADC : IBADC
bits : 0 - 15 (16 bit)
access : read-write
AD conversion result of c-phase current
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICADC : ICADC
bits : 0 - 15 (16 bit)
access : read-write
DC supply voltage (voltage _V_ _ maximum voltage * 2^15)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDC : VDC
bits : 0 - 15 (16 bit)
access : read-write
d-axis current (current _A_ _ maximum current * 2^31)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-write
q-axis current (current _A_ _ maximum current * 2^31)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQ : IQ
bits : 0 - 31 (32 bit)
access : read-write
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