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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCTRL_CH0

UNIT_CH0

PCTRL_CH1

PATTERN_CH1

CYCLE_CH1

DUTY_CH1

UNIT_CH1

STATE_CH1

INTCLR_CH1

STATE_CH0

INTCLR_CH0

PCTRL_CH2

PATTERN_CH2

CYCLE_CH2

DUTY_CH2

UNIT_CH2

STATE_CH2

INTCLR_CH2

PCTRL_CH3

PATTERN_CH3

CYCLE_CH3

DUTY_CH3

UNIT_CH3

STATE_CH3

INTCLR_CH3

PATTERN_CH0

CYCLE_CH0

DUTY_CH0


PCTRL_CH0

PWM CH0 enable control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCTRL_CH0 PCTRL_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE unit_en Pol IntMask

ENABLE : PWM channel enable (R/W) 0: Stop (default) 1: Start Please set cycle and duty before this is set to start.
bits : 0 - 0 (1 bit)
access : read-write

unit_en : 1-s timer enable (R/W) 0: Timer OFF (default) 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
bits : 1 - 2 (2 bit)
access : read-write

Pol : PWM output polarity control (R/W) 0: Polarity inversion OFF (default) 1: Polarity inversion ON
bits : 2 - 4 (3 bit)
access : read-write

IntMask : PWM interrupt mask (R/W) 0: Interrupt output enabled 1: Interrupt disabled (default)
bits : 3 - 6 (4 bit)
access : read-write


UNIT_CH0

PWM CH0 rhythm counter period set
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNIT_CH0 UNIT_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unit_startvalue

Unit_startvalue : Counter value setting to count 50 ms 0x0665 for 32.768 kHz (default) 0x9EB0F for 13 MHz Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
bits : 0 - 19 (20 bit)
access : read-write


PCTRL_CH1

PWM CH1 enable control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCTRL_CH1 PCTRL_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE unit_en Pol IntMask

ENABLE : PWM channel enable (R/W) 0: Stop (default) 1: Start Please set cycle and duty before this is set to start.
bits : 0 - 0 (1 bit)
access : read-write

unit_en : 1-s timer enable (R/W) 0: Timer OFF (default) 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
bits : 1 - 2 (2 bit)
access : read-write

Pol : PWM output polarity control (R/W) 0: Polarity inversion OFF (default) 1: Polarity inversion ON
bits : 2 - 4 (3 bit)
access : read-write

IntMask : PWM interrupt mask (R/W) 0: Interrupt output enabled 1: Interrupt disabled (default)
bits : 3 - 6 (4 bit)
access : read-write


PATTERN_CH1

PWM CH1 output mask set
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATTERN_CH1 PATTERN_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rhythm_Pat

Rhythm_Pat : PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output) 1: Output mask OFF (PWM output) This has no effect when 1-s timer is OFF.
bits : 0 - 19 (20 bit)
access : read-write


CYCLE_CH1

PWM CH1 cycle set
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE_CH1 CYCLE_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cycle

cycle : Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
bits : 0 - 11 (12 bit)
access : read-write


DUTY_CH1

PWM CH1 duty set
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUTY_CH1 DUTY_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Duty

Duty : Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF) duty ratio = (this value)/(cycle + 1)
bits : 0 - 11 (12 bit)
access : read-write


UNIT_CH1

PWM CH1 rhythm counter period set
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNIT_CH1 UNIT_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unit_startvalue

Unit_startvalue : Counter value setting to count 50 ms 0x0665 for 32.768 kHz (default) 0x9EB0F for 13 MHz Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
bits : 0 - 19 (20 bit)
access : read-write


STATE_CH1

PWM CH1 status
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE_CH1 STATE_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int_state Pwm_state Timer_state

Int_state : INT status 0: Not interrupted 1: Interrupted This is cleared when INTClr bit 0 is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Pwm_state : Cycle counter status 0: ON 1: Idle
bits : 1 - 2 (2 bit)
access : read-write

Timer_state : 1-s timer status 0: ON 1: Idle
bits : 2 - 4 (3 bit)
access : read-write


INTCLR_CH1

PWM CH1 interrupt clear
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR_CH1 INTCLR_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntClr

IntClr : PWM interrupt clear register (initial 0, W) Writeing 1 to this register clears the interrupt status.
bits : 0 - 0 (1 bit)
access : read-write


STATE_CH0

PWM CH0 status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE_CH0 STATE_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int_state Pwm_state Timer_state

Int_state : INT status 0: Not interrupted 1: Interrupted This is cleared when INTClr bit 0 is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Pwm_state : Cycle counter status 0: ON 1: Idle
bits : 1 - 2 (2 bit)
access : read-write

Timer_state : 1-s timer status 0: ON 1: Idle
bits : 2 - 4 (3 bit)
access : read-write


INTCLR_CH0

PWM CH0 interrupt clear
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR_CH0 INTCLR_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntClr

IntClr : PWM interrupt clear register (initial 0, W) Writeing 1 to this register clears the interrupt status.
bits : 0 - 0 (1 bit)
access : read-write


PCTRL_CH2

PWM CH2 enable control
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCTRL_CH2 PCTRL_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE unit_en Pol IntMask

ENABLE : PWM channel enable (R/W) 0: Stop (default) 1: Start Please set cycle and duty before this is set to start.
bits : 0 - 0 (1 bit)
access : read-write

unit_en : 1-s timer enable (R/W) 0: Timer OFF (default) 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
bits : 1 - 2 (2 bit)
access : read-write

Pol : PWM output polarity control (R/W) 0: Polarity inversion OFF (default) 1: Polarity inversion ON
bits : 2 - 4 (3 bit)
access : read-write

IntMask : PWM interrupt mask (R/W) 0: Interrupt output enabled 1: Interrupt disabled (default)
bits : 3 - 6 (4 bit)
access : read-write


PATTERN_CH2

PWM CH2 output mask set
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATTERN_CH2 PATTERN_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rhythm_Pat

Rhythm_Pat : PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output) 1: Output mask OFF (PWM output) This has no effect when 1-s timer is OFF.
bits : 0 - 19 (20 bit)
access : read-write


CYCLE_CH2

PWM CH2 cycle set
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE_CH2 CYCLE_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cycle

cycle : Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
bits : 0 - 11 (12 bit)
access : read-write


DUTY_CH2

PWM CH2 duty set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUTY_CH2 DUTY_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Duty

Duty : Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF) duty ratio = (this value)/(cycle + 1)
bits : 0 - 11 (12 bit)
access : read-write


UNIT_CH2

PWM CH2 rhythm counter period set
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNIT_CH2 UNIT_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unit_startvalue

Unit_startvalue : Counter value setting to count 50 ms 0x0665 for 32.768 kHz (default) 0x9EB0F for 13 MHz Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
bits : 0 - 19 (20 bit)
access : read-write


STATE_CH2

PWM CH2 status
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE_CH2 STATE_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int_state Pwm_state Timer_state

Int_state : INT status 0: Not interrupted 1: Interrupted This is cleared when INTClr bit 0 is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Pwm_state : Cycle counter status 0: ON 1: Idle
bits : 1 - 2 (2 bit)
access : read-write

Timer_state : 1-s timer status 0: ON 1: Idle
bits : 2 - 4 (3 bit)
access : read-write


INTCLR_CH2

PWM CH2 interrupt clear
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR_CH2 INTCLR_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntClr

IntClr : PWM interrupt clear register (initial 0, W) Writeing 1 to this register clears the interrupt status.
bits : 0 - 0 (1 bit)
access : read-write


PCTRL_CH3

PWM CH3 enable control
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCTRL_CH3 PCTRL_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE unit_en Pol IntMask

ENABLE : PWM channel enable (R/W) 0: Stop (default) 1: Start Please set cycle and duty before this is set to start.
bits : 0 - 0 (1 bit)
access : read-write

unit_en : 1-s timer enable (R/W) 0: Timer OFF (default) 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
bits : 1 - 2 (2 bit)
access : read-write

Pol : PWM output polarity control (R/W) 0: Polarity inversion OFF (default) 1: Polarity inversion ON
bits : 2 - 4 (3 bit)
access : read-write

IntMask : PWM interrupt mask (R/W) 0: Interrupt output enabled 1: Interrupt disabled (default)
bits : 3 - 6 (4 bit)
access : read-write


PATTERN_CH3

PWM CH3 output mask set
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATTERN_CH3 PATTERN_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rhythm_Pat

Rhythm_Pat : PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output) 1: Output mask OFF (PWM output) This has no effect when 1-s timer is OFF.
bits : 0 - 19 (20 bit)
access : read-write


CYCLE_CH3

PWM CH3 cycle set
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE_CH3 CYCLE_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cycle

cycle : Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
bits : 0 - 11 (12 bit)
access : read-write


DUTY_CH3

PWM CH3 duty set
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUTY_CH3 DUTY_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Duty

Duty : Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF) duty ratio = (this value)/(cycle + 1)
bits : 0 - 11 (12 bit)
access : read-write


UNIT_CH3

PWM CH3 rhythm counter period set
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNIT_CH3 UNIT_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unit_startvalue

Unit_startvalue : Counter value setting to count 50 ms 0x0665 for 32.768 kHz (default) 0x9EB0F for 13 MHz Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
bits : 0 - 19 (20 bit)
access : read-write


STATE_CH3

PWM CH3 status
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE_CH3 STATE_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int_state Pwm_state Timer_state

Int_state : INT status 0: Not interrupted 1: Interrupted This is cleared when INTClr bit 0 is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Pwm_state : Cycle counter status 0: ON 1: Idle
bits : 1 - 2 (2 bit)
access : read-write

Timer_state : 1-s timer status 0: ON 1: Idle
bits : 2 - 4 (3 bit)
access : read-write


INTCLR_CH3

PWM CH3 interrupt clear
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR_CH3 INTCLR_CH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntClr

IntClr : PWM interrupt clear register (initial 0, W) Writeing 1 to this register clears the interrupt status.
bits : 0 - 0 (1 bit)
access : read-write


PATTERN_CH0

PWM CH0 output mask set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATTERN_CH0 PATTERN_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rhythm_Pat

Rhythm_Pat : PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output) 1: Output mask OFF (PWM output) This has no effect when 1-s timer is OFF.
bits : 0 - 19 (20 bit)
access : read-write


CYCLE_CH0

PWM CH0 cycle set
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE_CH0 CYCLE_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cycle

cycle : Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
bits : 0 - 11 (12 bit)
access : read-write


DUTY_CH0

PWM CH0 duty set
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUTY_CH0 DUTY_CH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Duty

Duty : Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF) duty ratio = (this value)/(cycle + 1)
bits : 0 - 11 (12 bit)
access : read-write



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