CONTROL

INTCONTROL

INTSTATUS

TIMINGCONTROL2

TXRXLENGTH

TIMINGCONTROL

TXDATA

RXDATA

SETACT : Set operation mode (R/W) 0: Configuration mode 1: Active mode (default)
bits : 1 - 2 (2 bit)
access : read-write

SPSCKPH : Specify serial clock phase (R/W) 0: Sampling at the first edge (default) 1: Sampling at the second edge
bits : 5 - 10 (6 bit)
access : read-write

SPSCKPL : Specify serial clock polarity (R/W) 0: Sampling at high (default) 1: Sampling at low
bits : 6 - 12 (7 bit)
access : read-write

SPDIR : Specify LSB/MSB first (R/W) 0: MSB first (default) 1: LSB first
bits : 7 - 14 (8 bit)
access : read-write

SPCSEN0 : Enable CS (R/W) 0: Disable 1: Enable (default)
bits : 8 - 16 (9 bit)
access : read-write

SPCSPL0 : Set CS polarity (R/W) 0: Low active (default) 1: High active
bits : 12 - 24 (13 bit)
access : read-write

SLAVE : Set master/slave mode (R/W) 0: Master mode (default) 1: Slave mode
bits : 31 - 62 (32 bit)
access : read-write

TXCLR : Clear TX FIFO (R/W) 0: Do not clear (default) 1: Clear After claer, this register becomes 0.
bits : 12 - 24 (13 bit)
access : read-write

RXCLR : Clear RX FIFO (R/W) 0: Do not clear (default) 1: Clear After claer, this register becomes 0.
bits : 20 - 40 (21 bit)
access : read-write

TXFUL : Read the status of TX FIFO (R) 0: TX FIFO is full. 1: TX FIFO is not full.
bits : 8 - 16 (9 bit)
access : read-only

RXEMP : Read the status of RX FIFO (R) 0: RX FIFO is empty. 1: RX FIFO is not empty.
bits : 9 - 18 (10 bit)
access : read-only

SIFACT : Read the status of serial interface (R) 0: Idle (default) 1: Operating
bits : 11 - 22 (12 bit)
access : read-only

TXNUM : Read deta length in TX FIFO (R) 0000: 0 (default) 0001: 1 ... 0111: 7 1000: 8 Others: Don't care
bits : 24 - 51 (28 bit)
access : read-only

RXNUM : Read deta length in RX FIFO (R) 0000: 0 (default) 0001: 1 ... 0111: 7 1000: 8 Others: Don't care
bits : 28 - 59 (32 bit)
access : read-only

ADDSPLDLY : Add sampling delay of RX data (R/W) 01: 1 clk delay (fixed)
bits : 16 - 33 (18 bit)
access : read-write

TxLEN : Set the length of Tx data length 00-02: Forbidden 03: 4bit 04: 5bit ... 1E: 31bit 1F: 32bit
bits : 0 - 4 (5 bit)
access : read-write

Reserved1 : Do not change the values.
bits : 5 - 12 (8 bit)
access : read-write

RxLEN : Set the length of Rx data length 00-02: Forbidden. 03: 4bit 04: 5bit ... 1E:31bit 1F:32bit
bits : 8 - 20 (13 bit)
access : read-write

Reserved0 : Do not change the values.
bits : 13 - 44 (32 bit)
access : read-write

BASE : Set frequency devisor (R/W) 0: Not allowed 1-255: Allowed f_SPI = 13/(devisor x 2) MHz e.g. when devisor = 1, f_SPI = 6.5 MHz.
bits : 8 - 23 (16 bit)
access : read-write

TX : Set TX data (R/W) Default value is zero.
bits : 0 - 15 (16 bit)
access : read-write

BYTE : Set transfer byte length (R/W) 00: 1 byte (default) 01: 2 bytes 10: 3 bytes (valid for read) 11: 4 bytes (valid for read)
bits : 16 - 33 (18 bit)
access : read-write

CMD : Set transfer command (R/W) 0: Write (default) 1: Read
bits : 18 - 36 (19 bit)
access : read-write

CONT : Set continuous transfer (R/W) 0: Deassert CS per word (default) 1: Keep CS between words
bits : 19 - 38 (20 bit)
access : read-write

WRBIT : Set valid TX bit length (R/W) 0x0: The setting at bit[17:16] is applied (default). 0x1: 1 bit 0x2: 2 bit ... 0xF: 15 bit
bits : 20 - 43 (24 bit)
access : read-write

LEN : Default value is zero. When CMD is write (bit[18] = 0), set TX options (R/W). bit[31:26] Reserved bit[25] SPI DO polarity (0: L, 1: H) bit[24] SPI DO output status (0: keep the last data, 1: output H/L set at bit 25) When CMD is read (bit[18] = 1), set RX data length (R/W). bit[31:24] RX data length (unit is defined at bit[17:16])
bits : 24 - 55 (32 bit)
access : read-write

RX : Get RX data (R) When data is 24 bit length, [31:24] = 0x00 (default). When data is 16 bit length, [31:16] = 0x0000. When data is 8 bit length, [31:8] = 0x000000.
bits : 0 - 31 (32 bit)
access : read-only