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address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IntStatus0 : DMAC ch0 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 0 - 0 (1 bit)
access : read-only
IntStatus1 : DMAC ch1 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 1 - 2 (2 bit)
access : read-only
IntStatus2 : DMAC ch2 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 2 - 4 (3 bit)
access : read-only
IntStatus3 : DMAC ch3 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 3 - 6 (4 bit)
access : read-only
IntStatus4 : DMAC ch4 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 4 - 8 (5 bit)
access : read-only
IntStatus5 : DMAC ch5 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 5 - 10 (6 bit)
access : read-only
IntStatus6 : DMAC ch6 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
bits : 6 - 12 (7 bit)
access : read-only
Interrupt Error Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IntErrClr0 : Clear DMAC ch0 DMA error interrupt. 0: Invalid. 1: Clear
bits : 0 - 0 (1 bit)
access : read-write
IntErrClr1 : Clear DMAC ch1 DMA error interrupt. 0: Invalid. 1: Clear
bits : 1 - 2 (2 bit)
access : read-write
IntErrClr2 : Clear DMAC ch2 DMA error interrupt. 0: Invalid. 1: Clear
bits : 2 - 4 (3 bit)
access : read-write
IntErrClr3 : Clear DMAC ch3 DMA error interrupt. 0: Invalid. 1: Clear
bits : 3 - 6 (4 bit)
access : read-write
IntErrClr4 : Clear DMAC ch4 DMA error interrupt. 0: Invalid. 1: Clear
bits : 4 - 8 (5 bit)
access : read-write
IntErrClr5 : Clear DMAC ch5 DMA error interrupt. 0: Invalid. 1: Clear
bits : 5 - 10 (6 bit)
access : read-write
IntErrClr6 : Clear DMAC ch6 DMA error interrupt. 0: Invalid. 1: Clear
bits : 6 - 12 (7 bit)
access : read-write
Channel0 Source Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel0 is disabled on DMA_ch0_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel0 Destination Address Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel0 is disabled on DMA_ch0_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel0 Linked ListItem Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel0 Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat.
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte.
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel0 Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable.. 0: enable the interrupt. 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Channel1 Source Address Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel1 is disabled on DMA_ch1_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel1 Destination Address Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel1 is disabled on DMA_ch1_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel1 Linked ListItem Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel1 Control Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel1 Configuration Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config.. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable.. 0: enable the interrupt. 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Raw Interrupt Terminal Count Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RawIntTCStatus0 : Unmasked DMAC ch0 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 0 - 0 (1 bit)
access : read-only
RawIntTCStatus1 : Unmasked DMAC ch1 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 1 - 2 (2 bit)
access : read-only
RawIntTCStatus2 : Unmasked DMAC ch2 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 2 - 4 (3 bit)
access : read-only
RawIntTCStatus3 : Unmasked DMAC ch3 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 3 - 6 (4 bit)
access : read-only
RawIntTCStatus4 : Unmasked DMAC ch4 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 4 - 8 (5 bit)
access : read-only
RawIntTCStatus5 : Unmasked DMAC ch5 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 5 - 10 (6 bit)
access : read-only
RawIntTCStatus6 : Unmasked DMAC ch6 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 6 - 12 (7 bit)
access : read-only
Channel2 Source Address Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel2 is disabled on DMA_ch2_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel2 Destination Address Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel2 is disabled on DMA_ch2_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel2 Linked ListItem Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel2 Control Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel2 Configuration Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable.. 0: enable the interrupt. 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Channel3 Source Address Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel3 is disabled on DMA_ch3_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel3 Destination Address Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel3 is disabled on DMA_ch3_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel3 Linked ListItem Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel3 Control Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel3 Configuration Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Raw Interrupt Error Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RawIntErrStatus0 : Unmasked DMAC ch0 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 0 - 0 (1 bit)
access : read-only
RawIntErrStatus1 : Unmasked DMAC ch1 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 1 - 2 (2 bit)
access : read-only
RawIntErrStatus2 : Unmasked DMAC ch2 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 2 - 4 (3 bit)
access : read-only
RawIntErrStatus3 : Unmasked DMAC ch3 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 3 - 6 (4 bit)
access : read-only
RawIntErrStatus4 : Unmasked DMAC ch4 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 4 - 8 (5 bit)
access : read-only
RawIntErrStatus5 : Unmasked DMAC ch5 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 5 - 10 (6 bit)
access : read-only
RawIntErrStatus6 : Unmasked DMAC ch6 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 6 - 12 (7 bit)
access : read-only
Channel4 Source Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel4 is disabled on DMA_ch4_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel4 Destination Address Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel4 is disabled on DMA_ch4_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel4 Linked ListItem Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel4 Control Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel4 Configuration Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Channel5 Source Address Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel5 is disabled on DMA_ch5_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel5 Destination Address Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel5 is disabled on DMA_ch5_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel5 Linked ListItem Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel5 Control Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel5 Configuration Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Enabled Channel Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EnabledChannel0 : Enable/Disable DMAC ch0. 0: Disable. 1: Enable
bits : 0 - 0 (1 bit)
access : read-only
EnabledChannel1 : Enable/Disable DMAC ch1. 0: Disable. 1: Enable
bits : 1 - 2 (2 bit)
access : read-only
EnabledChannel2 : Enable/Disable DMAC ch2. 0: Disable. 1: Enable
bits : 2 - 4 (3 bit)
access : read-only
EnabledChannel3 : Enable/Disable DMAC ch3. 0: Disable. 1: Enable
bits : 3 - 6 (4 bit)
access : read-only
EnabledChannel4 : Enable/Disable DMAC ch4. 0: Disable. 1: Enable
bits : 4 - 8 (5 bit)
access : read-only
EnabledChannel5 : Enable/Disable DMAC ch5. 0: Disable. 1: Enable
bits : 5 - 10 (6 bit)
access : read-only
EnabledChannel6 : Enable/Disable DMAC ch6. 0: Disable. 1: Enable
bits : 6 - 12 (7 bit)
access : read-only
Channel6 Source Address Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SrcAddr : Set DMA source address. Please set this value when channel6 is disabled on DMA_ch6_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel6 Destination Address Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DestAddr : Set DMA destination address. Please set this value when channel6 is disabled on DMA_ch6_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel6 Linked ListItem Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLI : Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
bits : 0 - 31 (32 bit)
access : read-write
Channel6 Control Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TransferSize : Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
bits : 0 - 11 (12 bit)
access : read-write
SBSize : Set source burst size. Same as DBSize
bits : 12 - 26 (15 bit)
access : read-write
DBSize : Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
bits : 15 - 32 (18 bit)
access : read-write
SWidth : Set source bit width. Same as DWidth
bits : 18 - 38 (21 bit)
access : read-write
DWidth : Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
bits : 21 - 44 (24 bit)
access : read-write
SI : Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
bits : 26 - 52 (27 bit)
access : read-write
DI : Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
bits : 27 - 54 (28 bit)
access : read-write
I : Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
bits : 31 - 62 (32 bit)
access : read-write
Channel6 Configuration Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
bits : 0 - 0 (1 bit)
access : read-write
SrcPeripheral : DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
bits : 1 - 5 (5 bit)
access : read-write
DestPeripheral : DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
bits : 6 - 15 (10 bit)
access : read-write
FlowContrl : Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
bits : 11 - 24 (14 bit)
access : read-write
IE : DMA error interrupt enable. 0: enable the interrupt 1: disable the interrupt
bits : 14 - 28 (15 bit)
access : read-write
ITC : DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
bits : 15 - 30 (16 bit)
access : read-write
L : Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
bits : 16 - 32 (17 bit)
access : read-write
A : Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
bits : 17 - 34 (18 bit)
access : read-write
H : Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
bits : 18 - 36 (19 bit)
access : read-write
Software Burtst Request Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SoftBReq0 : Set DMA burst request for peripheral number 0. 0: Invalid request. 1: Occur request
bits : 0 - 0 (1 bit)
access : read-write
SoftBReq2 : Set DMA burst request for peripheral number 2. 0: Invalid request. 1: Occur request
bits : 2 - 4 (3 bit)
access : read-write
SoftBReq4 : Set DMA burst request for peripheral number 4. 0: Invalid request. 1: Occur request
bits : 4 - 8 (5 bit)
access : read-write
SoftBReq6 : Set DMA burst request for peripheral number 6. 0: Invalid request. 1: Occur request
bits : 6 - 12 (7 bit)
access : read-write
SoftBReq8 : Set DMA burst request for peripheral number 8. 0: Invalid request. 1: Occur request
bits : 8 - 16 (9 bit)
access : read-write
SoftBReq10 : Set DMA burst request for peripheral number 10. 0: Invalid request. 1: Occur request
bits : 10 - 20 (11 bit)
access : read-write
Software Single Request Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SoftSReq1 : Set DMA single request for peripheral number 1. 0: Invalid request. 1: Occur request
bits : 1 - 2 (2 bit)
access : read-write
SoftSReq3 : Set DMA single request for peripheral number 3. 0: Invalid request. 1: Occur request
bits : 3 - 6 (4 bit)
access : read-write
SoftSReq5 : Set DMA single request for peripheral number 5. 0: Invalid request. 1: Occur request
bits : 5 - 10 (6 bit)
access : read-write
SoftSReq7 : Set DMA single request for peripheral number 7. 0: Invalid request. 1: Occur request
bits : 7 - 14 (8 bit)
access : read-write
SoftSReq9 : Set DMA single request for peripheral number 9. 0: Invalid request. 1: Occur request
bits : 9 - 18 (10 bit)
access : read-write
SoftSReq11 : Set DMA single request for peripheral number 11. 0: Invalid request. 1: Occur request
bits : 11 - 22 (12 bit)
access : read-write
SoftSReq12 : Set DMA single request for peripheral number 12. 0: Invalid request. 1: Occur request
bits : 12 - 24 (13 bit)
access : read-write
Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : Control DMA circuit. 0: Halt. 1: Active. Set 1 to read/write DMAC registers.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt Terminal Count Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IntTCStatus0 : DMAC ch0 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 0 - 0 (1 bit)
access : read-only
IntTCStatus1 : DMAC ch1 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 1 - 2 (2 bit)
access : read-only
IntTCStatus2 : DMAC ch2 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 2 - 4 (3 bit)
access : read-only
IntTCStatus3 : DMAC ch3 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 3 - 6 (4 bit)
access : read-only
IntTCStatus4 : DMAC ch4 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 4 - 8 (5 bit)
access : read-only
IntTCStatus5 : DMAC ch5 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 5 - 10 (6 bit)
access : read-only
IntTCStatus6 : DMAC ch6 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
bits : 6 - 12 (7 bit)
access : read-only
Interrupt Terminal Count Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IntTCClear0 : Clear DMAC ch0 DMA done interrupt. 0: Invalid. 1: Clear
bits : 0 - 0 (1 bit)
access : read-only
IntTCClear1 : Clear DMAC ch1 DMA done interrupt. 0: Invalid. 1: Clear
bits : 1 - 2 (2 bit)
access : read-only
IntTCClear2 : Clear DMAC ch2 DMA done interrupt. 0: Invalid. 1: Clear
bits : 2 - 4 (3 bit)
access : read-only
IntTCClear3 : Clear DMAC ch3 DMA done interrupt. 0: Invalid. 1: Clear
bits : 3 - 6 (4 bit)
access : read-only
IntTCClear4 : Clear DMAC ch4 DMA done interrupt. 0: Invalid. 1: Clear
bits : 4 - 8 (5 bit)
access : read-only
IntTCClear5 : Clear DMAC ch5 DMA done interrupt. 0: Invalid. 1: Clear
bits : 5 - 10 (6 bit)
access : read-only
IntTCClear6 : Clear DMAC ch6 DMA done interrupt. 0: Invalid. 1: Clear
bits : 6 - 12 (7 bit)
access : read-only
Interrupt Error Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IntErrStatus0 : DMAC ch0 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 0 - 0 (1 bit)
access : read-only
IntErrStatus1 : DMAC ch1 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 1 - 2 (2 bit)
access : read-only
IntErrStatus2 : DMAC ch2 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 2 - 4 (3 bit)
access : read-only
IntErrStatus3 : DMAC ch3 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 3 - 6 (4 bit)
access : read-only
IntErrStatus4 : DMAC ch4 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 4 - 8 (5 bit)
access : read-only
IntErrStatus5 : DMAC ch5 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 5 - 10 (6 bit)
access : read-only
IntErrStatus6 : DMAC ch6 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
bits : 6 - 12 (7 bit)
access : read-only
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