\n

UART2

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UART_RBR_THR

UART_LFCR

UART_OVCR

UART_CWTCR

UART_IBRD

UART_FBRD

UART_ICR

UART_ILSR

UART_IER


UART_RBR_THR

Receiver Buffer Register/Transmitter Holding Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_RBR_THR UART_RBR_THR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBR_THR

RBR_THR : Tx/Rx Data
bits : 0 - 7 (8 bit)
access : read-write


UART_LFCR

Line and FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_LFCR UART_LFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxOutEn RxParityEn TxParityEn ParitySel StopSel InitUART TimerEnable ClkSel RxFIFOSel RxFIFOEn TxFIFOEn RxDMAEn TxDMAEn CTSEn RTSEn UARTRXMSK

TxOutEn : Tx Output enable/disable
bits : 0 - 0 (1 bit)
access : read-write

RxParityEn : Rx Data parity enable/disable
bits : 1 - 2 (2 bit)
access : read-write

TxParityEn : Tx Data parity enable/disable
bits : 2 - 4 (3 bit)
access : read-write

ParitySel : Select Parity bit (odd or even)
bits : 3 - 6 (4 bit)
access : read-write

StopSel : Select Stop bit(1bit or 2bit)
bits : 4 - 8 (5 bit)
access : read-write

InitUART : Initialize Sample Counter
bits : 5 - 10 (6 bit)
access : read-write

TimerEnable : Tx Timer Enable/Disable
bits : 6 - 12 (7 bit)
access : read-write

ClkSel : Select Clock for BaudRate
bits : 7 - 14 (8 bit)
access : read-write

RxFIFOSel : Select Rx FIFO Watermark Level
bits : 8 - 17 (10 bit)
access : read-write

RxFIFOEn : RxFIFO Enable/Disable
bits : 10 - 20 (11 bit)
access : read-write

TxFIFOEn : TxFIFO Enable/Disable
bits : 11 - 22 (12 bit)
access : read-write

RxDMAEn : RxDMA Request output enable
bits : 14 - 28 (15 bit)
access : read-write

TxDMAEn : TxDMA Request output enable
bits : 15 - 30 (16 bit)
access : read-write

CTSEn : Enable CTS Flow Control
bits : 16 - 32 (17 bit)
access : read-write

RTSEn : Enable RTS Flow Control
bits : 17 - 34 (18 bit)
access : read-write

UARTRXMSK : Rx Data Mask
bits : 18 - 36 (19 bit)
access : read-write


UART_OVCR

Sampling Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_OVCR UART_OVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVSMPCYC STDETCYC

OVSMPCYC : Oversample cycles setting
bits : 0 - 3 (4 bit)
access : read-write

STDETCYC : Start bit detect cycles for UART Rx Data
bits : 4 - 10 (7 bit)
access : read-write


UART_CWTCR

CWT Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_CWTCR UART_CWTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TimStartValue RxDataMon

TimStartValue : UART Receive Timer value
bits : 0 - 15 (16 bit)
access : read-write

RxDataMon : Monitor data existance info after Character Inteval Timeout
bits : 16 - 32 (17 bit)
access : read-write


UART_IBRD

Baud Rate Setting Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_IBRD UART_IBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUDINT

BAUDINT : UART Baudrate Integer divisor value
bits : 0 - 15 (16 bit)
access : read-write


UART_FBRD

Baud Rate Decimal Setting Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_FBRD UART_FBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFBRD

UFBRD : UART Baudrate Decimal Setting
bits : 0 - 5 (6 bit)
access : read-write


UART_ICR

Interrupt Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_ICR UART_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FramingErrorclr OverrunErrorclr ParityErrorclr DataSentclr TxDataEMPTYclr RxDataReadyclr TimeOutclr TxDataCompIntClr

FramingErrorclr : Clear Framing Error Interrupt
bits : 0 - 0 (1 bit)
access : read-write

OverrunErrorclr : Clear OverrunError Interrupt
bits : 1 - 2 (2 bit)
access : read-write

ParityErrorclr : Clear ParityError Interrupt
bits : 2 - 4 (3 bit)
access : read-write

DataSentclr : Clear DataSent Interrupt
bits : 3 - 6 (4 bit)
access : read-write

TxDataEMPTYclr : Clear TxDataEMPTY Interrupt
bits : 4 - 8 (5 bit)
access : read-write

RxDataReadyclr : Clear RxDataReady Interrupt
bits : 5 - 10 (6 bit)
access : read-write

TimeOutclr : Clear CWT Time Out Interrupt
bits : 6 - 12 (7 bit)
access : read-write

TxDataCompIntClr : Clear TxDataComp Interrupt
bits : 10 - 20 (11 bit)
access : read-write


UART_ILSR

Interrupt and Line Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_ILSR UART_ILSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FramingError OverrunError ParityError DataSent TxDataEMPTY RxDataReady TimeOut OVCRWriteBusy TxDataCompint RxBusy TxBusy RxFC TxFC

FramingError : FramingError Interrupt Status
bits : 0 - 0 (1 bit)
access : read-write

OverrunError : OverrunError Interrupt Status
bits : 1 - 2 (2 bit)
access : read-write

ParityError : ParityErrorr Interrupt Status
bits : 2 - 4 (3 bit)
access : read-write

DataSent : Data Sent Interrupt Status
bits : 3 - 6 (4 bit)
access : read-write

TxDataEMPTY : TxDataEMPTY Interrupt Status
bits : 4 - 8 (5 bit)
access : read-write

RxDataReady : RxDataReady Interupt Status
bits : 5 - 10 (6 bit)
access : read-write

TimeOut : CWT TimeOut Interrupt Status
bits : 6 - 12 (7 bit)
access : read-write

OVCRWriteBusy : Status of OVCR Write
bits : 7 - 14 (8 bit)
access : read-write

TxDataCompint : Tx Data Complete Interrupt
bits : 10 - 20 (11 bit)
access : read-write

RxBusy : Indicates if Rx working
bits : 14 - 28 (15 bit)
access : read-write

TxBusy : Indicates is Tx working
bits : 15 - 30 (16 bit)
access : read-write

RxFC : Count in Rx FIFO
bits : 16 - 36 (21 bit)
access : read-write

TxFC : Count in Tx FIFO
bits : 24 - 52 (29 bit)
access : read-write


UART_IER

Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_IER UART_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FramingErrorEN OverrunErrorEN ParityErrorEN DataSentEN TxDataEMPTYEN RxDataReadyEN TimeOutEN TxDataCompEN

FramingErrorEN : FramingError Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

OverrunErrorEN : OverrunError Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

ParityErrorEN : ParityError Interrupt Enable
bits : 2 - 4 (3 bit)
access : read-write

DataSentEN : DataSent Interrupt Enable
bits : 3 - 6 (4 bit)
access : read-write

TxDataEMPTYEN : TxDataEMPTY Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write

RxDataReadyEN : RxDataReady Interrupt Enable
bits : 5 - 10 (6 bit)
access : read-write

TimeOutEN : CWT TimeOut Interrupt Enable
bits : 6 - 12 (7 bit)
access : read-write

TxDataCompEN : TxDataComp Interrupt Enable
bits : 10 - 20 (11 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.