SPI_CONTROL

SPI_INTCONTROL

SPI_INTSTATUS

SPI_TIMINGCONTROL2

SPI_TXWAITTIMER0

SPI_TXWAITTIMER1

SPI_TXRXLENGTH

SPI_TIMINGCONTROL

SPI_TXDATA

SPI_RXDATA

SETACT : Set operation mode (R/W). 0: Configuration mode. 1: Active mode (default)
bits : 1 - 2 (2 bit)
access : read-write

SPSCKPH : Specify serial clock phase (R/W). 0: Sampling at the first edge (default). 1: Sampling at the second edge
bits : 5 - 10 (6 bit)
access : read-write

SPSCKPL : Specify serial clock polarity (R/W). 0: Sampling at high (default). 1: Sampling at low
bits : 6 - 12 (7 bit)
access : read-write

SPDIR : Specify LSB/MSB first (R/W). 0: MSB first (default). 1: LSB first
bits : 7 - 14 (8 bit)
access : read-write

SPCSEN0 : Enable CS (R/W). 0: Disable. 1: Enable (default)
bits : 8 - 16 (9 bit)
access : read-write

SPCSPL0 : Set CS polarity (R/W). 0: Low active (default). 1: High active
bits : 12 - 24 (13 bit)
access : read-write

SLAVE : Set master/slave mode (R/W). 0: Master mode (default). 1: Slave mode
bits : 31 - 62 (32 bit)
access : read-write

INTTX : TX FIFO interrupt. Asserted when there are datas more than [10:8]. 0: Disable interrupt. 1: Enable interrupt.
bits : 0 - 0 (1 bit)
access : read-write

INTRX : RX FIFO interrupt. Asserted when there are datas more than [18:16]. 0: Disable interrupt. 1: Enable interrupt.
bits : 1 - 2 (2 bit)
access : read-write

INTCTX0 : TX FIFO Overrun interrupt. 0: Disable interrupt. 1: Enable interrupt.
bits : 2 - 4 (3 bit)
access : read-write

INTCRX0 : RX FIFO Overrun interrupt. 0: Disable interrupt. 1: Enable interrupt.
bits : 3 - 6 (4 bit)
access : read-write

INTCPS : Serial Tx Complete interrupt. 0: Disable interrupt. 1: Enable interrupt.
bits : 4 - 8 (5 bit)
access : read-write

INTCTIM0 : Serial Tx Wait timer 0 interrupt. 0: Disable interrupt. 1: Enable interrupt.
bits : 5 - 10 (6 bit)
access : read-write

INTCTIM1 : Serial Tx Wait timer1 interrupt. 0: Disable interrupt. 1: Enable interrupt.
bits : 6 - 12 (7 bit)
access : read-write

INTCTXUR : Serial Under-run interrupt. 0: Disable interrupt. 1: Enable interrupt.
bits : 7 - 14 (8 bit)
access : read-write

TXINUM : Water mark for TX FIFO interrupt. 000: more than 1 data. 001: more than 2 data. 010: more than 3 data. 011: more than 4 data. 100: more than 5 data. 101: more than 6 data. 110: more than 7 data. 111: more than 8 data
bits : 8 - 18 (11 bit)
access : read-write

INTCTXCOMP : Set Tx complete interrupt. 0: Disable interrupt. 1: Enable interrupt
bits : 11 - 22 (12 bit)
access : read-write

TXCLR : Clear TX FIFO (R/W). 0: Do not clear (default). 1: Clear After claer, this register becomes 0.
bits : 12 - 24 (13 bit)
access : read-write

INTCTXCOMPSEL : Tx complete interrupt select bit. Selects the interrupt for bit 10 of interrupt status register. 0: SPI Tx complete status. 1: SPI Tx complete including SPI DMA TX
bits : 15 - 30 (16 bit)
access : read-write

RXINUM : Watermark for Rx FIFO interrupt. 000: more than 1 data. 001: more than 2 data. 010: more than 3 data. 011: more than 4 data. 100: more than 5 data. 101: more than 6 data. 110: more than 7 data. 111: more than 8 data
bits : 16 - 34 (19 bit)
access : read-write

RXCLR : Clear RX FIFO (R/W). 0: Do not clear (default). 1: Clear After claer, this register becomes 0.
bits : 20 - 40 (21 bit)
access : read-write

INTSTX : Reads Tx FIFO interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 0 - 0 (1 bit)
access : read-write

INTSRX : Reads Rx FIFO interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 1 - 2 (2 bit)
access : read-write

INTSTX0 : Reads Tx Fifo Overrun interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 2 - 4 (3 bit)
access : read-write

INTSRX0 : Reads Rx Fifo Overrun interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 3 - 6 (4 bit)
access : read-write

INTSSPS : Reads Tx send complete interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 4 - 8 (5 bit)
access : read-write

INTSTIM0 : Reads Tx Wait timer0 interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 5 - 10 (6 bit)
access : read-write

INTSTIM1 : Reads Tx Wait timer1 interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 6 - 12 (7 bit)
access : read-write

INTSTXUR : Reads Tx Underrun interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
bits : 7 - 14 (8 bit)
access : read-write

TXFUL : Read the status of TX FIFO (R). 0: TX FIFO is full. 1: TX FIFO is not full.
bits : 8 - 16 (9 bit)
access : read-only

RXEMP : Read the status of RX FIFO (R). 0: RX FIFO is empty. 1: RX FIFO is not empty.
bits : 9 - 18 (10 bit)
access : read-only

TXCOMP : Read the status of TX complete interrupt. 0: Exists Interrupt factor. 1: No Interrupt factor.
bits : 10 - 20 (11 bit)
access : read-write

SIFACT : Read the status of serial interface (R). 0: Idle (default). 1: Operating
bits : 11 - 22 (12 bit)
access : read-only

TXWPT : Tx FIFO Read pointer info
bits : 12 - 26 (15 bit)
access : read-write

TXRPT : Tx FIFO Read pointer info
bits : 15 - 32 (18 bit)
access : read-write

RXWPT : Rx FIFO Write pointer info
bits : 18 - 38 (21 bit)
access : read-write

RXRPT : Rx FIFO Read pointer info
bits : 21 - 44 (24 bit)
access : read-write

TXNUM : Read deta length in TX FIFO (R). 0000: 0 (default). 0001: 1. ... 0111: 7. 1000: 8. Others: Don't care
bits : 24 - 51 (28 bit)
access : read-only

RXNUM : Read deta length in RX FIFO (R). 0000: 0 (default). 0001: 1. ... 0111: 7. 1000: 8. Others: Don't care
bits : 28 - 59 (32 bit)
access : read-only

SDOMD : Seriaou output adjust enable/disable. 0: Disable. 1: Enable
bits : 0 - 0 (1 bit)
access : read-write

SCSMD : Chip Select output adjust timing enable/disable. 0: disable. 1: enable
bits : 1 - 2 (2 bit)
access : read-write

DOADJ : Adjust Serial data and chip select. 0: No adjustment. Other: value
bits : 8 - 21 (14 bit)
access : read-write

ADDSPLDLY : Add sampling delay of RX data (R/W). 01: 1 clk delay (fixed)
bits : 16 - 33 (18 bit)
access : read-write

TIM0B : Value for Tx Waittimer0.
bits : 0 - 19 (20 bit)
access : read-write

TIM1B : Value for Tx Waittimer1.
bits : 0 - 19 (20 bit)
access : read-write

TxLEN : Set the length of Tx data length. 00-02: Forbidden. 03: 4bit. 04: 5bit. ... 1E: 31bit. 1F: 32bit
bits : 0 - 4 (5 bit)
access : read-write

RxLEN : Set the length of Rx data length. 00-02: Forbidden. 03: 4bit. 04: 5bit. ... 1E:31bit. 1F:32bit
bits : 8 - 20 (13 bit)
access : read-write

PRS : Pre-Scaler Setting. 00: Communication clock x 1/1. 01: Communication clock x 1/2. 10: Communication clock x 1/4. 11: Communication clock x 1/8
bits : 0 - 1 (2 bit)
access : read-write

SMPMD : Sampling Modulation Mode.
bits : 2 - 4 (3 bit)
access : read-write

SCKMD : Serial Clock Mode. Enable/Disable Serial Clock modulation mode. 0: Disabled. 1: Enabled
bits : 3 - 6 (4 bit)
access : read-write

CSDIS : Chip Select disable parameter. If set, CS will be deasserted at least clock*(this value +1). 0: No deassert. 1-15: Deassert
bits : 4 - 11 (8 bit)
access : read-write

BASE : Frequency divider. 0: Forbidden. 1-255: value
bits : 8 - 23 (16 bit)
access : read-write

SMPADJ : Sampling clock adjustment. 0: forbidden. 1-63: setting value
bits : 16 - 37 (22 bit)
access : read-write

EXCKR : SCK will be output after the deassert of CS. The duration is set on [7:4]. 0: Disable clock extension. 1: Enable clock extension.
bits : 22 - 44 (23 bit)
access : read-write

EXCKW : Set Write clock extension. SCK will be output after the deassert of CS. The duration is set on [7:4]. 0: Disable clock extension. 1: Enable clock extension.
bits : 23 - 46 (24 bit)
access : read-write

SCKADJ : Serial Clock Adjustment. Set a value less than [15:8]. 0: Forbidden. 1-63: settingvalue
bits : 24 - 53 (30 bit)
access : read-write

div : Change the division setting.
bits : 30 - 60 (31 bit)
access : read-write

TX : Set TX data (R/W) Default value is zero.
bits : 0 - 15 (16 bit)
access : read-write

BYTE : Set transfer byte length (R/W). 00: 1 byte (default). 01: 2 bytes. 10: 3 bytes (valid for read). 11: 4 bytes (valid for read)
bits : 16 - 33 (18 bit)
access : read-write

CMD : Set transfer command (R/W). 0: Write (default). 1: Read
bits : 18 - 36 (19 bit)
access : read-write

CONT : Set continuous transfer (R/W). 0: Deassert CS per word (default). 1: Keep CS between words
bits : 19 - 38 (20 bit)
access : read-write

WRBIT : Set valid TX bit length (R/W). 0x0: The setting at bit[17:16] is applied (default). 0x1: 1 bit. 0x2: 2 bit. ... 0xF: 15 bit
bits : 20 - 43 (24 bit)
access : read-write

LEN : Default value is zero. When CMD is write (bit[18] = 0), set TX options (R/W). bit[31:26] Reserved bit[25] SPI DO polarity (0: L, 1: H) bit[24] SPI DO output status (0: keep the last data, 1: output H/L set at bit 25). When CMD is read (bit[18] = 1), set RX data length (R/W). bit[31:24] RX data length (unit is defined at bit[17:16])
bits : 24 - 55 (32 bit)
access : read-write

RX : Get RX data (R). When data is 24 bit length, [31:24] = 0x00 (default). When data is 16 bit length, [31:16] = 0x0000. When data is 8 bit length, [31:8] = 0x000000.
bits : 0 - 31 (32 bit)
access : read-only