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CLOCK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CG_DIVNUM3

CG_DIVNUM4

CG_DIVNUM5

CG_CLK_CTRL

CG_CLK_CTRL2

CG_PWM_CTRL

CG_CG_CTRL

CG_WD_INIT

CG_WD_CURNT


CG_DIVNUM3

Division ratio for PWM1 and PWM0 config
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_DIVNUM3 CG_DIVNUM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0_DIVNUM PWM1_DIVNUM

PWM0_DIVNUM : Division ratio of 32MHz clock to generate PWM0 clock. PWM0 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
bits : 0 - 11 (12 bit)
access : read-write

PWM1_DIVNUM : Division ratio of 32MHz clock to generate PWM1 clock. PWM1 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
bits : 16 - 43 (28 bit)
access : read-write


CG_DIVNUM4

Division ratio for PWM3 and PWM2 config
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_DIVNUM4 CG_DIVNUM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM2_DIVNUM PWM3_DIVNUM

PWM2_DIVNUM : Division ratio of 32MHz clock to generate PWM2 clock. PWM2 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
bits : 0 - 11 (12 bit)
access : read-write

PWM3_DIVNUM : Division ratio of 32MHz clock to generate PWM3 clock. PWM3 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
bits : 16 - 43 (28 bit)
access : read-write


CG_DIVNUM5

Division ratio for GPADC config
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_DIVNUM5 CG_DIVNUM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPADC_DIVNUM

GPADC_DIVNUM : Division ratio of 32MHz clock to generate GPADC clock. frequency divider = (value+1)*2
bits : 0 - 8 (9 bit)
access : read-write


CG_CLK_CTRL

SPI Clock control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_CLK_CTRL CG_CLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BitClkEn SyncClkEn Uart1ClkEn LELLCClkEn MPHYDMACClkEn FUSEClkEn I2CClkEn SPIClkEn RFBClkEn QSPIClkEn DMAClkEn TimerClkEn GPIOClkEn OUIClkEn ESGClkEn PPLClkEn

BitClkEn : Enable Bit Clock
bits : 0 - 0 (1 bit)
access : read-write

SyncClkEn : Enable Sync Clock
bits : 1 - 2 (2 bit)
access : read-write

Uart1ClkEn : Enable UART1 Clock
bits : 2 - 4 (3 bit)
access : read-write

LELLCClkEn : Enable LELLC Clock
bits : 4 - 8 (5 bit)
access : read-write

MPHYDMACClkEn : Enable MPHDMAC Clock
bits : 5 - 10 (6 bit)
access : read-write

FUSEClkEn : Enable FUSE Clock
bits : 7 - 14 (8 bit)
access : read-write

I2CClkEn : Enable I2C Clock
bits : 8 - 16 (9 bit)
access : read-write

SPIClkEn : Enable SPI clock (R/W) 1: Enable clock 0: Disable clock (default)
bits : 9 - 18 (10 bit)
access : read-write

RFBClkEn : Enable RFB Clock Enable
bits : 10 - 20 (11 bit)
access : read-write

QSPIClkEn : Enable QSPI Clock
bits : 11 - 22 (12 bit)
access : read-write

DMAClkEn : ENable DMA Clock
bits : 12 - 24 (13 bit)
access : read-write

TimerClkEn : Enable Timer Clock
bits : 13 - 26 (14 bit)
access : read-write

GPIOClkEn : Enable GPIO Clock
bits : 24 - 48 (25 bit)
access : read-write

OUIClkEn : Enable OIU Clock
bits : 25 - 50 (26 bit)
access : read-write

ESGClkEn : Enable ESG Clock
bits : 26 - 52 (27 bit)
access : read-write

PPLClkEn : Enable PPL Clock
bits : 29 - 58 (30 bit)
access : read-write


CG_CLK_CTRL2

PWM Clock Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_CLK_CTRL2 CG_CLK_CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0ClkEn PWM1ClkEn PWM2ClkEn PWM3ClkEn PWM0SlpClkEn PWM1SlpClkEn PWM2SlpClkEn PWM3SlpClkEn GPADCClkEn Uart2ClkEn SPI2ClkEn I2C2ClkEn

PWM0ClkEn : Enable PWM ch 0 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 0 - 0 (1 bit)
access : read-write

PWM1ClkEn : Enable PWM ch 1 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 1 - 2 (2 bit)
access : read-write

PWM2ClkEn : Enable PWM ch 2 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 2 - 4 (3 bit)
access : read-write

PWM3ClkEn : Enable PWM ch 3 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 3 - 6 (4 bit)
access : read-write

PWM0SlpClkEn : Enable PWM ch 0 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 4 - 8 (5 bit)
access : read-write

PWM1SlpClkEn : Enable PWM ch 1 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 5 - 10 (6 bit)
access : read-write

PWM2SlpClkEn : Enable PWM ch 2 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 6 - 12 (7 bit)
access : read-write

PWM3SlpClkEn : Enable PWM ch 3 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
bits : 7 - 14 (8 bit)
access : read-write

GPADCClkEn : Enable GPADC Clock
bits : 8 - 16 (9 bit)
access : read-write

Uart2ClkEn : Enable UART2 Clock
bits : 9 - 18 (10 bit)
access : read-write

SPI2ClkEn : Enable SPI2 Clock
bits : 10 - 20 (11 bit)
access : read-write

I2C2ClkEn : Enable I2C2 Clock
bits : 11 - 22 (12 bit)
access : read-write


CG_PWM_CTRL

PWM clock mode set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_PWM_CTRL CG_PWM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0ClkSel PWM1ClkSel PWM2ClkSel PWM3ClkSel

PWM0ClkSel : Select PWM0 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM0SlpClkEn and PWM0ClkEn before changing this register.
bits : 0 - 0 (1 bit)
access : read-write

PWM1ClkSel : Select PWM1 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM1SlpClkEn and PWM1ClkEn before changing this register.
bits : 1 - 2 (2 bit)
access : read-write

PWM2ClkSel : Select PWM2 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM2SlpClkEn and PWM2ClkEn before changing this register.
bits : 2 - 4 (3 bit)
access : read-write

PWM3ClkSel : Select PWM3 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM3SlpClkEn and PWM3ClkEn before changing this register.
bits : 3 - 6 (4 bit)
access : read-write


CG_CG_CTRL

ckgn config register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_CG_CTRL CG_CG_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WdCountSTOP SoftReset

WdCountSTOP : Start or stop WDT counter. 1: Stop counter. 0: Start counter. When set 1, WDT counter suspends. When set 0, WDT counter resumes. During the system state is low power mode, WDT does not count.
bits : 2 - 4 (3 bit)
access : read-write

SoftReset : Soft-Reset control 1: Soft-Reset 0: No change
bits : 5 - 10 (6 bit)
access : read-write


CG_WD_INIT

Watchdog initial register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_WD_INIT CG_WD_INIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDINIT

WDINIT : Set initial value of WDT counter. This value can be set from 0x1(30.5 micro seconds) to 0x1FFFFF.(64 seconds). Setting time is calculated as below: setting time = (this value) * 30.5 micro seconds. When you update this value, please wait for more than 2 clocks of SleepClk(32kHz clock) since the previous change. When the system wakes up from low power mode, WDT counter is set this value.
bits : 0 - 20 (21 bit)
access : read-write


CG_WD_CURNT

Watchdog current register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CG_WD_CURNT CG_WD_CURNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCURNT

WDTCURNT : Watchdog current value. When the system wakes up from low power mode, this value becomes WDINIT value.
bits : 0 - 20 (21 bit)
access : read-write



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