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SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

CIDR

WUER

WUSR

RSER

RSSR

PRER1

PRER2

PER1

PER2

PCER1

PCER2

SMR

CSCR

SCCR

CMR

NMIR

COR

PLLCON

VDCCON

LVDCON

SRCR

EOSCR

EMODR

MCCR1

MCCR2

MCCR3

DBCLK1

DBCLK2

MCCR4

CIDR2


CIDR

Chip ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR CIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WUER

Wakeup Source Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUER WUER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDWUE WDTWUE GPIOAWUE GPIOBWUE GPIOCWUE GPIODWUE

LVDWUE : LVDWUE
bits : 0 - 0 (1 bit)

WDTWUE : WDTWUE
bits : 1 - 1 (1 bit)

GPIOAWUE : GPIOAWUE
bits : 8 - 8 (1 bit)

GPIOBWUE : GPIOBWUE
bits : 9 - 9 (1 bit)

GPIOCWUE : GPIOCWUE
bits : 10 - 10 (1 bit)

GPIODWUE : GPIODWUE
bits : 11 - 11 (1 bit)


WUSR

Wakeup Source Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUSR WUSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDWU WDTWU GPIOAWU GPIOBWU GPIOCWU GPIODWU

LVDWU : LVDWU
bits : 0 - 0 (1 bit)

WDTWU : WDTWU
bits : 1 - 1 (1 bit)

GPIOAWU : GPIOAWU
bits : 8 - 8 (1 bit)

GPIOBWU : GPIOBWU
bits : 9 - 9 (1 bit)

GPIOCWU : GPIOCWU
bits : 10 - 10 (1 bit)

GPIODWU : GPIODWU
bits : 11 - 11 (1 bit)


RSER

Reset Source Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSER RSER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRST XFRST MCKFRST WDTRST SWRST CPURST PINRST

LVDRST : LVD reset enable
bits : 0 - 0 (1 bit)

XFRST : external OSC clock failed enable
bits : 1 - 1 (1 bit)

MCKFRST : MCLK failed reset enable
bits : 2 - 2 (1 bit)

WDTRST : watch dog reset enable
bits : 3 - 3 (1 bit)

SWRST : software reset enable
bits : 4 - 4 (1 bit)

CPURST : CPU request reset enable
bits : 5 - 5 (1 bit)

PINRST : external pin reset enable
bits : 6 - 6 (1 bit)


RSSR

Reset Source Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSSR RSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRST XFRST MCKFRST WDTRST SWRST CPURST PINRST PORST

LVDRST : lvd reset status
bits : 0 - 0 (1 bit)

XFRST : clock failed reset status
bits : 1 - 1 (1 bit)

MCKFRST : MCLK failed reset status
bits : 2 - 2 (1 bit)

WDTRST : watchdog timer reset status
bits : 3 - 3 (1 bit)

SWRST : software reset status
bits : 4 - 4 (1 bit)

CPURST : cpu request reset status
bits : 5 - 5 (1 bit)

PINRST : extenral pin reset status
bits : 6 - 6 (1 bit)

PORST : power on reset status
bits : 7 - 7 (1 bit)


PRER1

Peripheral Reset Enable Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRER1 PRER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCU FMC WDT PCU DMA GPIOA GPIOB GPIOC GPIOD TIMER0 TIMER1 TIMER2 TIMER3 TIMER8 TIMER9

SCU : Power Management Unit Reset
bits : 0 - 0 (1 bit)

FMC : Flash Memory controll Reset
bits : 1 - 1 (1 bit)

WDT : Watch Dog Timer Reset
bits : 2 - 2 (1 bit)

PCU : Port controll Reset
bits : 3 - 3 (1 bit)

DMA : DMA Reset
bits : 4 - 4 (1 bit)

GPIOA : GPIOA Reset
bits : 8 - 8 (1 bit)

GPIOB : GPIOB Reset
bits : 9 - 9 (1 bit)

GPIOC : GPIOC Reset
bits : 10 - 10 (1 bit)

GPIOD : GPIOD Reset
bits : 11 - 11 (1 bit)

TIMER0 : TIMER0 reset
bits : 16 - 16 (1 bit)

TIMER1 : TIMER1 Reset
bits : 17 - 17 (1 bit)

TIMER2 : TIMER2 Reset
bits : 18 - 18 (1 bit)

TIMER3 : TIMER3 Reset
bits : 19 - 19 (1 bit)

TIMER8 : TIMER8 Reset
bits : 24 - 24 (1 bit)

TIMER9 : TIMER9 Reset
bits : 25 - 25 (1 bit)


PRER2

Peripheral Reset Enable Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRER2 PRER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 I2C0 UART0 UART1 MPWM0 ADC0 ADC1

SPI0 : SPI0 Reset
bits : 0 - 0 (1 bit)

I2C0 : I2C0 Reset
bits : 4 - 4 (1 bit)

UART0 : UART0 Reset
bits : 8 - 8 (1 bit)

UART1 : UART1
bits : 9 - 9 (1 bit)

MPWM0 : MPWM0 Reset
bits : 16 - 16 (1 bit)

ADC0 : ADC0 Reset
bits : 20 - 20 (1 bit)

ADC1 : ADC1 Reset
bits : 21 - 21 (1 bit)


PER1

Peripheral Enable Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER1 PER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA GPIOA GPIOB GPIOC GPIOD TIMER0 TIMER1 TIMER2 TIMER3 TIMER8 TIMER9

DMA : DMA Function Enable
bits : 4 - 4 (1 bit)

GPIOA : GPIOA
bits : 8 - 8 (1 bit)

GPIOB : GPIOB
bits : 9 - 9 (1 bit)

GPIOC : GPIOC
bits : 10 - 10 (1 bit)

GPIOD : GPIOD
bits : 11 - 11 (1 bit)

TIMER0 : TIMER0
bits : 16 - 16 (1 bit)

TIMER1 : TIMER1
bits : 17 - 17 (1 bit)

TIMER2 : TIMER2
bits : 18 - 18 (1 bit)

TIMER3 : TIMER3
bits : 19 - 19 (1 bit)

TIMER8 : TIMER8 Enable
bits : 24 - 24 (1 bit)

TIMER9 : TIMER9 Enable
bits : 25 - 25 (1 bit)


PER2

Peripheral Enable Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER2 PER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 I2C0 UART0 UART1 MPWM0 ADC0 ADC1

SPI0 : SPI0 Enable
bits : 0 - 0 (1 bit)

I2C0 : I2C0 Enable
bits : 4 - 4 (1 bit)

UART0 : UART0 Enable
bits : 8 - 8 (1 bit)

UART1 : UART1 Enable
bits : 9 - 9 (1 bit)

MPWM0 : MPWM0 Enable
bits : 16 - 16 (1 bit)

ADC0 : ADC0
bits : 20 - 20 (1 bit)

ADC1 : ADC1
bits : 21 - 21 (1 bit)


PCER1

Peripheral Clock Enable Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCER1 PCER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA GPIOA GPIOB GPIOC GPIOD TIMER0 TIMER1 TIMER2 TIMER3 TIMER8 TIMER9

DMA : DMA Function Enable
bits : 4 - 4 (1 bit)

GPIOA : GPIOA
bits : 8 - 8 (1 bit)

GPIOB : GPIOB
bits : 9 - 9 (1 bit)

GPIOC : GPIOC
bits : 10 - 10 (1 bit)

GPIOD : GPIOD
bits : 11 - 11 (1 bit)

TIMER0 : TIMER0
bits : 16 - 16 (1 bit)

TIMER1 : TIMER1
bits : 17 - 17 (1 bit)

TIMER2 : TIMER2
bits : 18 - 18 (1 bit)

TIMER3 : TIMER3
bits : 19 - 19 (1 bit)

TIMER8 : TIMER8 Enable
bits : 24 - 24 (1 bit)

TIMER9 : TIMER9 Enable
bits : 25 - 25 (1 bit)


PCER2

Peripheral Clock Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCER2 PCER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 I2C0 UART0 UART1 MPWM0 ADC0 ADC1

SPI0 : SPI0 Enable
bits : 0 - 0 (1 bit)

I2C0 : I2C0 Enable
bits : 4 - 4 (1 bit)

UART0 : UART0 Enable
bits : 8 - 8 (1 bit)

UART1 : UART1 Enable
bits : 9 - 9 (1 bit)

MPWM0 : MPWM0 Enable
bits : 16 - 16 (1 bit)

ADC0 : ADC0
bits : 20 - 20 (1 bit)

ADC1 : ADC1
bits : 21 - 21 (1 bit)


SMR

System Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREVMODE

PREVMODE : PREVMODE
bits : 4 - 5 (2 bit)


CSCR

Clock Source Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCR CSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOSCCON RINGOSCCON

EOSCCON : External crystal OSC control
bits : 0 - 1 (2 bit)

RINGOSCCON : Internal ring OSC control
bits : 4 - 5 (2 bit)


SCCR

System Clock Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCR SCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCLKSEL FINSEL

MCLKSEL : System clock select
bits : 0 - 1 (2 bit)

FINSEL : PLL Input source FIN Select
bits : 2 - 2 (1 bit)


CMR

Clock Monitoring Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR CMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOSCSTS EOSCFAIL EOSCIE EOSCMNT MCLKSTS MCLKFAIL MCLKIE MCLKMNT MCLKREC

EOSCSTS : external OSC status
bits : 0 - 0 (1 bit)
access : read-write

EOSCFAIL : external OSC failed flag
bits : 1 - 1 (1 bit)
access : read-write

EOSCIE : external OSC failed interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

EOSCMNT : Externaler OSC monitor enable
bits : 3 - 3 (1 bit)
access : read-write

MCLKSTS : MCLK clock status
bits : 4 - 4 (1 bit)
access : read-write

MCLKFAIL : MCLK Failed flag
bits : 5 - 5 (1 bit)
access : read-write

MCLKIE : MCLK fail Interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

MCLKMNT : MCLK monitor enable
bits : 7 - 7 (1 bit)
access : read-write

MCLKREC : MCLK failed auto recovery
bits : 15 - 15 (1 bit)
access : read-only


NMIR

NMI Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMIR NMIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDEN MCLKFAILEN WDTEN OVPEN PROTEN LVDSTS MCLKFAILSTS WDTSTS OVPSTS PROTSTS ACCESSCODE

LVDEN : LVD Condition Enable
bits : 0 - 0 (1 bit)

MCLKFAILEN : MCLK Fail Condition Enable
bits : 1 - 1 (1 bit)

WDTEN : Watch Dog Interrupt Condition Enable
bits : 2 - 2 (1 bit)

OVPEN : Over Voltage Protection Condition Enable
bits : 3 - 3 (1 bit)

PROTEN : Protection Condition Enable
bits : 4 - 4 (1 bit)

LVDSTS : LVD Condition Status
bits : 8 - 8 (1 bit)

MCLKFAILSTS : MCLK Fail Condition Status
bits : 9 - 9 (1 bit)

WDTSTS : Watch Dog Interrupt Condition Status
bits : 10 - 10 (1 bit)

OVPSTS : Over Voltage Protection Condition Status
bits : 11 - 11 (1 bit)

PROTSTS : Protection Condition Status
bits : 12 - 12 (1 bit)

ACCESSCODE : Access Code
bits : 16 - 31 (16 bit)
access : write-only


COR

Clock Output Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COR COR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKODIV CLKOEN

CLKODIV : clock output divider value
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : clock output enable
bits : 4 - 4 (1 bit)
access : read-write


PLLCON

PLL Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCON PLLCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSTDIV FBCTRL PREDIV LOCK BYPASS PLLEN PLLRSTB

POSTDIV : post divider
bits : 0 - 3 (4 bit)
access : read-write

FBCTRL : Feedback control
bits : 4 - 7 (4 bit)
access : read-write

PREDIV : FIN pre divider
bits : 8 - 8 (1 bit)
access : read-write

LOCK : PLL Lock state
bits : 12 - 12 (1 bit)
access : read-only

BYPASS : FIN Bypass to FOUT
bits : 13 - 13 (1 bit)
access : read-write

PLLEN : PLL Enable
bits : 14 - 14 (1 bit)
access : read-write

PLLRSTB : PLL reset
bits : 15 - 15 (1 bit)
access : read-write


VDCCON

VDC Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDCCON VDCCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDCWDLY VDCDE VDCTRIM VDCTE

VDCWDLY : VDC warm up delay count
bits : 0 - 7 (8 bit)
access : read-write

VDCDE : VDCDE
bits : 8 - 8 (1 bit)
access : write-only

VDCTRIM : VDCTRIM
bits : 16 - 19 (4 bit)
access : read-write

VDCTE : VDC value enable
bits : 23 - 23 (1 bit)
access : write-only


LVDCON

LVD Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVDCON LVDCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDEN LVDLVL LVDSEL SELEN LVDTRIM LVDTE

LVDEN : LVDEN
bits : 0 - 0 (1 bit)

LVDLVL : LVDLVL
bits : 1 - 1 (1 bit)
access : read-only

LVDSEL : LVDSEL
bits : 8 - 9 (2 bit)

SELEN : SELEN
bits : 15 - 15 (1 bit)
access : write-only

LVDTRIM : LVDTRIM
bits : 16 - 17 (2 bit)

LVDTE : LVDTE
bits : 23 - 23 (1 bit)
access : write-only


SRCR

System Reset Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCR SRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST

SWRST : Internal soft reset activation
bits : 0 - 0 (1 bit)


EOSCR

External Oscillator Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EOSCR EOSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISEL ISELEN

ISEL : select current
bits : 8 - 9 (2 bit)
access : read-write

ISELEN : write enable for bit field ISEL
bits : 15 - 15 (1 bit)
access : write-only


EMODR

External Mode Status Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMODR EMODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOT

BOOT : boot pin level
bits : 0 - 0 (1 bit)


MCCR1

Miscellaneous Clock Control Register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR1 MCCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STDIV STCSEL

STDIV : systick divider
bits : 0 - 7 (8 bit)
access : read-write

STCSEL : systick clock source sel
bits : 8 - 10 (3 bit)
access : read-write


MCCR2

Miscellaneous Clock Control Register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR2 MCCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0DIV PWM0CSEL

PWM0DIV : PWM0 divider
bits : 0 - 7 (8 bit)

PWM0CSEL : pwm0 clock sel
bits : 8 - 10 (3 bit)


MCCR3

Miscellaneous Clock Control Register 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR3 MCCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTDIV WDTCSEL TEXT0DIV TEXT0CSEL

WDTDIV : WDT divider
bits : 0 - 7 (8 bit)

WDTCSEL : WDT clock sel
bits : 8 - 10 (3 bit)

TEXT0DIV : text0 divider
bits : 16 - 23 (8 bit)

TEXT0CSEL : text0 clock sel
bits : 24 - 26 (3 bit)


DBCLK1

Debounce Clock Control Register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLK1 DBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDIV PADCSEL PBDDIV PBDSEL

PADDIV : PORT A debounce divider
bits : 0 - 7 (8 bit)

PADCSEL : debouce clock for port A source clock sel
bits : 8 - 10 (3 bit)

PBDDIV : PORT B debounce divider
bits : 16 - 23 (8 bit)

PBDSEL : debouce clock for port B source clock sel
bits : 24 - 26 (3 bit)


DBCLK2

Debounce Clock Control Register 2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLK2 DBCLK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCDDIV PCDSEK PDDDIV PDDCSEL

PCDDIV : PORT C debounce divider
bits : 0 - 7 (8 bit)

PCDSEK : debouce clock for port C source clock sel
bits : 8 - 10 (3 bit)

PDDDIV : PORT D debounce divider
bits : 16 - 23 (8 bit)

PDDCSEL : debouce clock for port D source clock sel
bits : 24 - 26 (3 bit)


MCCR4

Miscellaneous Clock Control Register 4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR4 MCCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCCDIV ADCCSEL

ADCCDIV : ADC Clock N divider
bits : 16 - 23 (8 bit)

ADCCSEL : ADC clock source select bitl
bits : 24 - 26 (3 bit)


CIDR2

Chip ID 2 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR2 CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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