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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DR

TMR

DRTY

TICK

CRC

CFG

MR

BOOTCR

PROTECT

JTAGEN

CR

AR


DR

Flash Memory Data Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATA

FDATA : Flash PGM data
bits : 0 - 31 (32 bit)


TMR

Flash Memory Timer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR TMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR

TMR : Erase/PGM timer
bits : 0 - 15 (16 bit)


DRTY

Flash Memory Dirty bit Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRTY DRTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDRTY

FDRTY : Write any value,cache line fill falg will be cleared
bits : 0 - 31 (32 bit)


TICK

Flash Memory Tick Timer register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TICK TICK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTICK

FTICK : TICK
bits : 0 - 17 (18 bit)


CRC

Flash Memory CRC value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC CRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC

CRC : CRC16 Value
bits : 0 - 15 (16 bit)


CFG

Flash Memory Config value register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM CRCEN CRCINIT WAIT TMRCK HRESPD WRITEKEY

TRIM : Flash Trim Value
bits : 0 - 3 (4 bit)

CRCEN : Enable CRC on Flash Read
bits : 6 - 6 (1 bit)

CRCINIT : Initalize CRC Register
bits : 7 - 7 (1 bit)

WAIT : Wait Access for Flash
bits : 8 - 10 (3 bit)

TMRCK : Timer Clock Source
bits : 12 - 12 (1 bit)

HRESPD : HRESP Disable (Error Response Function)
bits : 15 - 15 (1 bit)

WRITEKEY : Write Key for access
bits : 16 - 31 (16 bit)


MR

Flash Memory Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACODE FMOD FEMOD TRM TRMEN AMBAEN VERIFY IDLE BOOT

ACODE : Flash Mode/Trim Mode
bits : 0 - 7 (8 bit)
access : read-write

FMOD : Flash Mode status
bits : 8 - 8 (1 bit)
access : read-only

FEMOD : Flash Mode entry status
bits : 9 - 9 (1 bit)
access : read-only

TRM : Trim Mode status
bits : 16 - 16 (1 bit)
access : read-only

TRMEN : Trim Mode entry status
bits : 17 - 17 (1 bit)
access : read-only

AMBAEN : AMBA mode enable
bits : 22 - 22 (1 bit)
access : read-write

VERIFY : Flash verify Mode enable status
bits : 23 - 23 (1 bit)
access : read-only

IDLE : Idle mode enable status
bits : 24 - 24 (1 bit)
access : read-only

BOOT : Boot Mode enable status
bits : 31 - 31 (1 bit)
access : read-only


BOOTCR

Boot ROM Remap Clear Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOTCR BOOTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOTROM

BOOTROM : Boot mode
bits : 0 - 0 (1 bit)


PROTECT

Write Protection Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP0 WP1 WP2 WP3 WP4 WP5 WP6 WP7 WP8 WP9 WP10 WP11 WP12 WP13 WP14 WP15 WRITE_KEY

WP0 : WP Block 0
bits : 0 - 0 (1 bit)

WP1 : WP Block 1
bits : 1 - 1 (1 bit)

WP2 : WP Block 2
bits : 2 - 2 (1 bit)

WP3 : WP Block 3
bits : 3 - 3 (1 bit)

WP4 : WP Block 4
bits : 4 - 4 (1 bit)

WP5 : WP Block 5
bits : 5 - 5 (1 bit)

WP6 : WP Block 6
bits : 6 - 6 (1 bit)

WP7 : WP Block 7
bits : 7 - 7 (1 bit)

WP8 : WP Block 8
bits : 8 - 8 (1 bit)

WP9 : WP Block 9
bits : 9 - 9 (1 bit)

WP10 : WP Block 10
bits : 10 - 10 (1 bit)

WP11 : WP Block 11
bits : 11 - 11 (1 bit)

WP12 : WP Block 12
bits : 12 - 12 (1 bit)

WP13 : WP Block 13
bits : 13 - 13 (1 bit)

WP14 : WP Block 14
bits : 14 - 14 (1 bit)

WP15 : WP Block 15
bits : 15 - 15 (1 bit)

WRITE_KEY : Write Key
bits : 24 - 31 (8 bit)


JTAGEN

JTAG Protection Control Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JTAGEN JTAGEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JTAGEN WRITE_KEY

JTAGEN : JTAG Enable
bits : 0 - 0 (1 bit)

WRITE_KEY : Write Key
bits : 24 - 31 (8 bit)


CR

Flash Memory Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBR ERS PGM PBLD WE PMODE AE PPGM OTPAE OTPBE PVER EVER VPPOUT TEST TIMER

PBR : page buffer reset
bits : 0 - 0 (1 bit)
access : read-write

ERS : program mode/erase mode Enable
bits : 1 - 1 (1 bit)
access : read-write

PGM : PGM
bits : 2 - 2 (1 bit)
access : read-write

PBLD : page buffer load
bits : 3 - 3 (1 bit)
access : read-write

WE : write Enable
bits : 4 - 4 (1 bit)
access : read-write

PMODE : Pmode Enable
bits : 5 - 5 (1 bit)
access : read-write

AE : All Erase
bits : 8 - 8 (1 bit)
access : read-only

PPGM : Pre PGM enable
bits : 9 - 9 (1 bit)
access : read-only

OTPAE : OTP area A enable
bits : 10 - 10 (1 bit)
access : read-only

OTPBE : OTP area B enable
bits : 11 - 11 (1 bit)
access : read-only

PVER : Program verify mode
bits : 13 - 13 (1 bit)
access : read-only

EVER : Erase verify Mode
bits : 14 - 14 (1 bit)
access : read-only

VPPOUT : Charge pump Vpp Output
bits : 15 - 15 (1 bit)
access : read-only

TEST : TEST
bits : 16 - 17 (2 bit)
access : read-only

TIMER : program timer enable
bits : 20 - 20 (1 bit)
access : read-only


AR

Flash Memory Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADDR

FADDR : 32K words address
bits : 0 - 13 (14 bit)



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