\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
DMA Controller Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : transfer Direction
bits : 1 - 1 (1 bit)
SIZE : Bus transfer size
bits : 2 - 3 (2 bit)
PERISEL : Peripheral Selection
bits : 8 - 11 (4 bit)
TRANSCNT : Numer of DMA transfer remained
bits : 16 - 27 (12 bit)
DMA Controller Status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA enable
bits : 0 - 0 (1 bit)
access : read-write
EOT : End of transfer
bits : 7 - 7 (1 bit)
access : read-only
DMA Controller Peripheral Address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAR : PAR
bits : 0 - 31 (32 bit)
DMA Controller Memory Address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : Memory address
bits : 0 - 15 (16 bit)
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