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address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
MPWM Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDOWN : PWM counter mode
bits : 0 - 0 (1 bit)
MCHMOD : Motor Control Mode
bits : 1 - 2 (2 bit)
BUP : Bottom match update mode
bits : 4 - 4 (1 bit)
TUP : Period match update mode
bits : 5 - 5 (1 bit)
UAO : update mode
bits : 7 - 7 (1 bit)
MOTORB : Normal/Motor mode
bits : 15 - 15 (1 bit)
MPWM Duty UH Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : duty of UH output
bits : 0 - 15 (16 bit)
MPWM Duty VH Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : duty of VH data
bits : 0 - 15 (16 bit)
MPWM Duty WH Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : duty of WH output
bits : 0 - 15 (16 bit)
MPWM Duty UL Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : duty of UL output
bits : 0 - 15 (16 bit)
MPWM Duty UL Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : duty of VL output
bits : 0 - 15 (16 bit)
MPWM Duty WL Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : duty of WL output
bits : 0 - 15 (16 bit)
MPWM Control Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMEN : PWM enable
bits : 0 - 0 (1 bit)
IRQN : IRQ interval Number
bits : 8 - 10 (3 bit)
MPWM Control Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSTART : PWM start
bits : 0 - 0 (1 bit)
HALT : PWM HALT
bits : 7 - 7 (1 bit)
MPWM Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DULIF : duty UL interrupt flag
bits : 0 - 0 (1 bit)
DVLIRQ : duty VL interrupt flag
bits : 1 - 1 (1 bit)
DWLIRQ : duty WL interrupt flag
bits : 2 - 2 (1 bit)
DUHIF : duty UH interrupt flag
bits : 3 - 3 (1 bit)
DVHIF : duty VH interrupt flag
bits : 4 - 4 (1 bit)
DWHIF : duty WH interrupt flag
bits : 5 - 5 (1 bit)
BOTIF : PWM bottom interrupt flag
bits : 6 - 6 (1 bit)
PRDIF : PWM period interrupt flag
bits : 7 - 7 (1 bit)
IRQCNT : PWM count number of period match
bits : 12 - 14 (3 bit)
DOWN : PWM count up/down
bits : 15 - 15 (1 bit)
MPWM Interrupt Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULIE : duty UL interrupt enable
bits : 0 - 0 (1 bit)
VLIE : duty VL interrupt enable
bits : 1 - 1 (1 bit)
WLIE : duty WL interrupt enable
bits : 2 - 2 (1 bit)
UHIE : duty UH interrupt enable
bits : 3 - 3 (1 bit)
VHIE : duty VH interrupt enable
bits : 4 - 4 (1 bit)
WHIE : duty WH interrupt enable
bits : 5 - 5 (1 bit)
BOTIE : bottom interrupt enable
bits : 6 - 6 (1 bit)
PRDIEN : Period interrupt enable
bits : 7 - 7 (1 bit)
MPWM Counter Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : pwm counter value
bits : 0 - 15 (16 bit)
MPWM Dead Time Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DT : dead time value
bits : 0 - 7 (8 bit)
DTCLK : dead time clk select
bits : 8 - 8 (1 bit)
PSHRT : Protect Short Condition
bits : 14 - 14 (1 bit)
DTEN : dead time Enable
bits : 15 - 15 (1 bit)
MPWM Output Level Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULL : U Low Output Level
bits : 0 - 0 (1 bit)
VLL : V Low Output Level
bits : 1 - 1 (1 bit)
WLL : W Low Output Level
bits : 2 - 2 (1 bit)
UHL : U High Output Level
bits : 3 - 3 (1 bit)
VHL : V High Output Level
bits : 4 - 4 (1 bit)
WHL : W High Output Level
bits : 5 - 5 (1 bit)
MPWM Protection control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPROTM : U phase Low protection output
bits : 0 - 0 (1 bit)
VLPROTM : V phase Low protection output
bits : 1 - 1 (1 bit)
WLPROTM : W phase Low protection output
bits : 2 - 2 (1 bit)
UHPROTM : U phase High protection output
bits : 3 - 3 (1 bit)
VHPROTM : V phase High protection output
bits : 4 - 4 (1 bit)
WHPROTM : W phase High protection output
bits : 5 - 5 (1 bit)
PROTIE : Protection Interrup Enable
bits : 7 - 7 (1 bit)
PROTD : Protection Input Debounce
bits : 8 - 10 (3 bit)
PROT0POL : Protection Input 0 Polarity
bits : 14 - 14 (1 bit)
PROT0EN : Protection Input 0 Enable
bits : 15 - 15 (1 bit)
MPWM Protection 0 Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPROT : U phase Low protection status
bits : 0 - 0 (1 bit)
VLPROT : V phase Low protection status
bits : 1 - 1 (1 bit)
WLPROT : W phase Low protection status
bits : 2 - 2 (1 bit)
UHPROT : U phase High protection status
bits : 3 - 3 (1 bit)
VHPROT : V phase High protection status
bits : 4 - 4 (1 bit)
WHPROT : W phase High protection status
bits : 5 - 5 (1 bit)
PROTIF : Protection Interrupt Flag
bits : 7 - 7 (1 bit)
PROTKEY : lock safety pattern to set or reset protection
bits : 8 - 15 (8 bit)
MPWM Protection control 1 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPROTM : U phase Low protection output
bits : 0 - 0 (1 bit)
VLPROTM : V phase Low protection output
bits : 1 - 1 (1 bit)
WLPROTM : W phase Low protection output
bits : 2 - 2 (1 bit)
UHPROTM : U phase High protection output
bits : 3 - 3 (1 bit)
VHPROTM : V phase High protection output
bits : 4 - 4 (1 bit)
WHPROTM : W phase High protection output
bits : 5 - 5 (1 bit)
PROTIE : Protection Interrup Enable
bits : 7 - 7 (1 bit)
PROTD : Protection Input Debounce
bits : 8 - 10 (3 bit)
PROT0POL : Protection Input 0 Polarity
bits : 14 - 14 (1 bit)
PROT0EN : Protection Input 0 Enable
bits : 15 - 15 (1 bit)
MPWM Protection 1 Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPROT : U phase Low protection status
bits : 0 - 0 (1 bit)
VLPROT : V phase Low protection status
bits : 1 - 1 (1 bit)
WLPROT : W phase Low protection status
bits : 2 - 2 (1 bit)
UHPROT : U phase High protection status
bits : 3 - 3 (1 bit)
VHPROT : V phase High protection status
bits : 4 - 4 (1 bit)
WHPROT : W phase High protection status
bits : 5 - 5 (1 bit)
PROTIF : Protection Interrupt Flag
bits : 7 - 7 (1 bit)
PROTKEY : lock safety pattern to set or reset protection
bits : 8 - 15 (8 bit)
MPWMn ADC Trigger Counter 1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)
ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)
ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)
MPWMn ADC Trigger Counter 2 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)
ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)
ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)
MPWMn ADC Trigger Counter 3 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)
ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)
ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)
MPWMn ADC Trigger Counter 4 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)
ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)
ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)
MPWMn ADC Trigger Counter 5 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)
ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)
ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)
MPWMn ADC Trigger Counter 6 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)
ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)
ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)
MPWM Force Output Level Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULFL : U Low Forced Output Level
bits : 0 - 0 (1 bit)
VLFL : V Low Forced Output Level
bits : 1 - 1 (1 bit)
WLFL : W Low Forced Output Level
bits : 2 - 2 (1 bit)
UHFL : U High Forced Output Level
bits : 3 - 3 (1 bit)
VHFL : V High Forced Output Level
bits : 4 - 4 (1 bit)
WHFL : W High Forced Output Level
bits : 5 - 5 (1 bit)
MPWM Period Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM period
bits : 0 - 15 (16 bit)
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