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MPWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

DUH

DVH

DWH

DUL

DVL

DWL

CR1

CR2

SR

IER

CNT

DTR

OLR

PCR0

PSR0

PCR1

PSR1

ATR1

ATR2

ATR3

ATR4

ATR5

ATR6

FOLR

PRD


MR

MPWM Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDOWN MCHMOD BUP TUP UAO MOTORB

UPDOWN : PWM counter mode
bits : 0 - 0 (1 bit)

MCHMOD : Motor Control Mode
bits : 1 - 2 (2 bit)

BUP : Bottom match update mode
bits : 4 - 4 (1 bit)

TUP : Period match update mode
bits : 5 - 5 (1 bit)

UAO : update mode
bits : 7 - 7 (1 bit)

MOTORB : Normal/Motor mode
bits : 15 - 15 (1 bit)


DUH

MPWM Duty UH Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUH DUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of UH output
bits : 0 - 15 (16 bit)


DVH

MPWM Duty VH Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVH DVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of VH data
bits : 0 - 15 (16 bit)


DWH

MPWM Duty WH Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWH DWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of WH output
bits : 0 - 15 (16 bit)


DUL

MPWM Duty UL Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUL DUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of UL output
bits : 0 - 15 (16 bit)


DVL

MPWM Duty UL Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVL DVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of VL output
bits : 0 - 15 (16 bit)


DWL

MPWM Duty WL Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWL DWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of WL output
bits : 0 - 15 (16 bit)


CR1

MPWM Control Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMEN IRQN

PWMEN : PWM enable
bits : 0 - 0 (1 bit)

IRQN : IRQ interval Number
bits : 8 - 10 (3 bit)


CR2

MPWM Control Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTART HALT

PSTART : PWM start
bits : 0 - 0 (1 bit)

HALT : PWM HALT
bits : 7 - 7 (1 bit)


SR

MPWM Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DULIF DVLIRQ DWLIRQ DUHIF DVHIF DWHIF BOTIF PRDIF IRQCNT DOWN

DULIF : duty UL interrupt flag
bits : 0 - 0 (1 bit)

DVLIRQ : duty VL interrupt flag
bits : 1 - 1 (1 bit)

DWLIRQ : duty WL interrupt flag
bits : 2 - 2 (1 bit)

DUHIF : duty UH interrupt flag
bits : 3 - 3 (1 bit)

DVHIF : duty VH interrupt flag
bits : 4 - 4 (1 bit)

DWHIF : duty WH interrupt flag
bits : 5 - 5 (1 bit)

BOTIF : PWM bottom interrupt flag
bits : 6 - 6 (1 bit)

PRDIF : PWM period interrupt flag
bits : 7 - 7 (1 bit)

IRQCNT : PWM count number of period match
bits : 12 - 14 (3 bit)

DOWN : PWM count up/down
bits : 15 - 15 (1 bit)


IER

MPWM Interrupt Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULIE VLIE WLIE UHIE VHIE WHIE BOTIE PRDIEN

ULIE : duty UL interrupt enable
bits : 0 - 0 (1 bit)

VLIE : duty VL interrupt enable
bits : 1 - 1 (1 bit)

WLIE : duty WL interrupt enable
bits : 2 - 2 (1 bit)

UHIE : duty UH interrupt enable
bits : 3 - 3 (1 bit)

VHIE : duty VH interrupt enable
bits : 4 - 4 (1 bit)

WHIE : duty WH interrupt enable
bits : 5 - 5 (1 bit)

BOTIE : bottom interrupt enable
bits : 6 - 6 (1 bit)

PRDIEN : Period interrupt enable
bits : 7 - 7 (1 bit)


CNT

MPWM Counter Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : pwm counter value
bits : 0 - 15 (16 bit)


DTR

MPWM Dead Time Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTR DTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT DTCLK PSHRT DTEN

DT : dead time value
bits : 0 - 7 (8 bit)

DTCLK : dead time clk select
bits : 8 - 8 (1 bit)

PSHRT : Protect Short Condition
bits : 14 - 14 (1 bit)

DTEN : dead time Enable
bits : 15 - 15 (1 bit)


OLR

MPWM Output Level Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OLR OLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULL VLL WLL UHL VHL WHL

ULL : U Low Output Level
bits : 0 - 0 (1 bit)

VLL : V Low Output Level
bits : 1 - 1 (1 bit)

WLL : W Low Output Level
bits : 2 - 2 (1 bit)

UHL : U High Output Level
bits : 3 - 3 (1 bit)

VHL : V High Output Level
bits : 4 - 4 (1 bit)

WHL : W High Output Level
bits : 5 - 5 (1 bit)


PCR0

MPWM Protection control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR0 PCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULPROTM VLPROTM WLPROTM UHPROTM VHPROTM WHPROTM PROTIE PROTD PROT0POL PROT0EN

ULPROTM : U phase Low protection output
bits : 0 - 0 (1 bit)

VLPROTM : V phase Low protection output
bits : 1 - 1 (1 bit)

WLPROTM : W phase Low protection output
bits : 2 - 2 (1 bit)

UHPROTM : U phase High protection output
bits : 3 - 3 (1 bit)

VHPROTM : V phase High protection output
bits : 4 - 4 (1 bit)

WHPROTM : W phase High protection output
bits : 5 - 5 (1 bit)

PROTIE : Protection Interrup Enable
bits : 7 - 7 (1 bit)

PROTD : Protection Input Debounce
bits : 8 - 10 (3 bit)

PROT0POL : Protection Input 0 Polarity
bits : 14 - 14 (1 bit)

PROT0EN : Protection Input 0 Enable
bits : 15 - 15 (1 bit)


PSR0

MPWM Protection 0 Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR0 PSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULPROT VLPROT WLPROT UHPROT VHPROT WHPROT PROTIF PROTKEY

ULPROT : U phase Low protection status
bits : 0 - 0 (1 bit)

VLPROT : V phase Low protection status
bits : 1 - 1 (1 bit)

WLPROT : W phase Low protection status
bits : 2 - 2 (1 bit)

UHPROT : U phase High protection status
bits : 3 - 3 (1 bit)

VHPROT : V phase High protection status
bits : 4 - 4 (1 bit)

WHPROT : W phase High protection status
bits : 5 - 5 (1 bit)

PROTIF : Protection Interrupt Flag
bits : 7 - 7 (1 bit)

PROTKEY : lock safety pattern to set or reset protection
bits : 8 - 15 (8 bit)


PCR1

MPWM Protection control 1 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR1 PCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULPROTM VLPROTM WLPROTM UHPROTM VHPROTM WHPROTM PROTIE PROTD PROT0POL PROT0EN

ULPROTM : U phase Low protection output
bits : 0 - 0 (1 bit)

VLPROTM : V phase Low protection output
bits : 1 - 1 (1 bit)

WLPROTM : W phase Low protection output
bits : 2 - 2 (1 bit)

UHPROTM : U phase High protection output
bits : 3 - 3 (1 bit)

VHPROTM : V phase High protection output
bits : 4 - 4 (1 bit)

WHPROTM : W phase High protection output
bits : 5 - 5 (1 bit)

PROTIE : Protection Interrup Enable
bits : 7 - 7 (1 bit)

PROTD : Protection Input Debounce
bits : 8 - 10 (3 bit)

PROT0POL : Protection Input 0 Polarity
bits : 14 - 14 (1 bit)

PROT0EN : Protection Input 0 Enable
bits : 15 - 15 (1 bit)


PSR1

MPWM Protection 1 Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR1 PSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULPROT VLPROT WLPROT UHPROT VHPROT WHPROT PROTIF PROTKEY

ULPROT : U phase Low protection status
bits : 0 - 0 (1 bit)

VLPROT : V phase Low protection status
bits : 1 - 1 (1 bit)

WLPROT : W phase Low protection status
bits : 2 - 2 (1 bit)

UHPROT : U phase High protection status
bits : 3 - 3 (1 bit)

VHPROT : V phase High protection status
bits : 4 - 4 (1 bit)

WHPROT : W phase High protection status
bits : 5 - 5 (1 bit)

PROTIF : Protection Interrupt Flag
bits : 7 - 7 (1 bit)

PROTKEY : lock safety pattern to set or reset protection
bits : 8 - 15 (8 bit)


ATR1

MPWMn ADC Trigger Counter 1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR1 ATR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR2

MPWMn ADC Trigger Counter 2 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR2 ATR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR3

MPWMn ADC Trigger Counter 3 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR3 ATR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR4

MPWMn ADC Trigger Counter 4 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR4 ATR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR5

MPWMn ADC Trigger Counter 5 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR5 ATR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR6

MPWMn ADC Trigger Counter 6 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR6 ATR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


FOLR

MPWM Force Output Level Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FOLR FOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULFL VLFL WLFL UHFL VHFL WHFL

ULFL : U Low Forced Output Level
bits : 0 - 0 (1 bit)

VLFL : V Low Forced Output Level
bits : 1 - 1 (1 bit)

WLFL : W Low Forced Output Level
bits : 2 - 2 (1 bit)

UHFL : U High Forced Output Level
bits : 3 - 3 (1 bit)

VHFL : V High Forced Output Level
bits : 4 - 4 (1 bit)

WHFL : W High Forced Output Level
bits : 5 - 5 (1 bit)


PRD

MPWM Period Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD PRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : PWM period
bits : 0 - 15 (16 bit)



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