\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Wakeup Source Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDWUE : LVDWUE
bits : 0 - 0 (1 bit)
WDTWUE : WDTWUE
bits : 1 - 1 (1 bit)
FRTWUE : FRTWUE
bits : 2 - 2 (1 bit)
GPIOAWUE : GPIOAWUE
bits : 8 - 8 (1 bit)
GPIOBWUE : GPIOBWUE
bits : 9 - 9 (1 bit)
GPIOCWUE : GPIOCWUE
bits : 10 - 10 (1 bit)
GPIODWUE : GPIODWUE
bits : 11 - 11 (1 bit)
Wakeup Source Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVDWU : LVDWU
bits : 0 - 0 (1 bit)
WDTWU : WDTWU
bits : 1 - 1 (1 bit)
FRTWU : FRTWU
bits : 2 - 2 (1 bit)
GPIOAWU : GPIOAWU
bits : 8 - 8 (1 bit)
GPIOBWU : GPIOBWU
bits : 9 - 9 (1 bit)
GPIOCWU : GPIOCWU
bits : 10 - 10 (1 bit)
GPIODWU : GPIODWU
bits : 11 - 11 (1 bit)
Reset Source Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDRST : LVD reset enable
bits : 0 - 0 (1 bit)
MOFRST : MOSC Clock fail reset enable
bits : 1 - 1 (1 bit)
MCKFRST : MCLK Clock fail reset enable
bits : 2 - 2 (1 bit)
WDTRST : watch dog reset enable
bits : 3 - 3 (1 bit)
SWRST : software reset enable
bits : 4 - 4 (1 bit)
CPURST : CPU request reset enable
bits : 5 - 5 (1 bit)
PINRST : external pin reset enable
bits : 6 - 6 (1 bit)
LOCKUPRST : CPU Lock up reset enable bit
bits : 7 - 7 (1 bit)
Reset Source Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDRST : lvd reset status
bits : 0 - 0 (1 bit)
MOFRST : MOSC Clock fail reset status
bits : 1 - 1 (1 bit)
MCKFRST : MCLK failed reset status
bits : 2 - 2 (1 bit)
WDTRST : watchdog timer reset status
bits : 3 - 3 (1 bit)
SWRST : software reset status
bits : 4 - 4 (1 bit)
CPURST : cpu request reset status
bits : 5 - 5 (1 bit)
PINRST : extenral pin reset status
bits : 6 - 6 (1 bit)
PORST : power on reset status
bits : 7 - 7 (1 bit)
LOCKUPRST : CPU Lock up reset status
bits : 8 - 8 (1 bit)
Peripheral Reset Enable Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCU : Power Management Unit Reset enable
bits : 0 - 0 (1 bit)
FMC : Flash Memory controller Reset enable
bits : 1 - 1 (1 bit)
WDT : WatchDog timer reset enable
bits : 2 - 2 (1 bit)
PCU : Port Controller unit reset enable
bits : 3 - 3 (1 bit)
DIV64 : DIV64 Reset enable
bits : 5 - 5 (1 bit)
GPIOA : GPIOA Reset enable
bits : 8 - 8 (1 bit)
GPIOB : GPIOB Reset enable
bits : 9 - 9 (1 bit)
GPIOC : GPIOC Reset enable
bits : 10 - 10 (1 bit)
GPIOD : GPIOD Reset enable
bits : 11 - 11 (1 bit)
TIMER0 : TIMER0 Reset enable
bits : 16 - 16 (1 bit)
TIMER1 : TIMER1 reset enable
bits : 17 - 17 (1 bit)
TIMER2 : TIMER2 Reset enable
bits : 18 - 18 (1 bit)
TIMER3 : TIMER3 Reset enable
bits : 19 - 19 (1 bit)
FRT : FRT Reset enable
bits : 26 - 26 (1 bit)
Peripheral Reset Enable Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI : SPI Reset enable
bits : 0 - 0 (1 bit)
I2C : I2C Reset enable
bits : 4 - 4 (1 bit)
UART0 : UART0 Reset enable
bits : 8 - 8 (1 bit)
UART1 : UART1 Reset enable
bits : 9 - 9 (1 bit)
MPWM : MPWM Reset enable
bits : 16 - 16 (1 bit)
ADC : ADC Reset enable
bits : 20 - 20 (1 bit)
Peripheral Enable Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV64 : DIV64
bits : 5 - 5 (1 bit)
GPIOA : GPIOA
bits : 8 - 8 (1 bit)
GPIOB : GPIOB
bits : 9 - 9 (1 bit)
GPIOC : GPIOC
bits : 10 - 10 (1 bit)
GPIOD : GPIOD
bits : 11 - 11 (1 bit)
TIMER0 : TIMER0
bits : 16 - 16 (1 bit)
TIMER1 : TIMER1
bits : 17 - 17 (1 bit)
TIMER2 : TIMER2
bits : 18 - 18 (1 bit)
TIMER3 : TIMER3
bits : 19 - 19 (1 bit)
FRT : FRT
bits : 26 - 26 (1 bit)
Peripheral Enable Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI : SPI Enable
bits : 0 - 0 (1 bit)
I2C : I2C
bits : 4 - 4 (1 bit)
UART0 : UART0
bits : 8 - 8 (1 bit)
UART1 : UART1
bits : 9 - 9 (1 bit)
MPWM : MPWM
bits : 16 - 16 (1 bit)
ADC : ADC
bits : 20 - 20 (1 bit)
Peripheral Clock Enable Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV64 : DIV64
bits : 5 - 5 (1 bit)
GPIOA : GPIOA clock enable
bits : 8 - 8 (1 bit)
GPIOB : GPIOB clock enable
bits : 9 - 9 (1 bit)
GPIOC : GPIOC clock enable
bits : 10 - 10 (1 bit)
GPIOD : GPIOD clock enable
bits : 11 - 11 (1 bit)
TIMER0 : TIMER0
bits : 16 - 16 (1 bit)
TIMER1 : TIMER1 clock enable
bits : 17 - 17 (1 bit)
TIMER2 : TIMER2 clock enable
bits : 18 - 18 (1 bit)
TIMER3 : Timer3 clock enable
bits : 19 - 19 (1 bit)
FRT : FRT clock enable
bits : 26 - 26 (1 bit)
Peripheral Clock Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI : SPI clock enable
bits : 0 - 0 (1 bit)
I2C : I2C clock enable
bits : 4 - 4 (1 bit)
UART0 : UART0
bits : 8 - 8 (1 bit)
UART1 : UART1 clock enable
bits : 9 - 9 (1 bit)
MPWM : MPWM clock enable
bits : 16 - 16 (1 bit)
ADC : ADC clock enable
bits : 20 - 20 (1 bit)
System Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREVMODE : PREVMODE
bits : 4 - 5 (2 bit)
access : read-only
VDCAON : VDCAON
bits : 8 - 8 (1 bit)
LSIAON : LSIAON
bits : 9 - 9 (1 bit)
Clock Source Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOSCCON : External crystal main oscillator control
bits : 0 - 1 (2 bit)
HSICON : High speed internal oscillator control
bits : 2 - 3 (2 bit)
LSICON : Low speed internal oscillator control
bits : 4 - 5 (2 bit)
SOSCCON : External crystal sub oscillator control
bits : 6 - 7 (2 bit)
System Clock Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKSEL : System clock select
bits : 0 - 2 (3 bit)
Clock Monitoring Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOSCSTS : external OSC status
bits : 0 - 0 (1 bit)
access : read-write
MOSCFAIL : external OSC failed flag
bits : 1 - 1 (1 bit)
access : read-write
MOSCIE : external OSC failed interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
MOSCMNT : External OSC monitor enable
bits : 3 - 3 (1 bit)
access : read-write
MCLKSTS : MCLK clock status
bits : 4 - 4 (1 bit)
access : read-write
MCLKFAIL : MCLK Failed flag
bits : 5 - 5 (1 bit)
access : read-write
MCLKIE : MCLK fail Interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
MCLKMNT : MCLK monitor enable
bits : 7 - 7 (1 bit)
access : read-write
SOSCSTS : Sub Oscillator clock status
bits : 8 - 8 (1 bit)
access : read-write
SOSCFAIL : Sub Oscillator fail interrupt flag
bits : 9 - 9 (1 bit)
access : read-write
SOSCIE : Sub Oscillator fail interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
SOSCMNT : Sub Oscillator monitoring enable
bits : 11 - 11 (1 bit)
access : read-write
MCLKREC : MCLK failed auto recovery
bits : 15 - 15 (1 bit)
access : read-write
NMI Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDEN : LVDEN
bits : 0 - 0 (1 bit)
MCLKFAILEN : MCLKFAILEN
bits : 1 - 1 (1 bit)
WDTINTEN : WDTINTEN
bits : 2 - 2 (1 bit)
OVPEN : OVPEN
bits : 3 - 3 (1 bit)
PROTEN : PROTEN
bits : 4 - 4 (1 bit)
LVDSTS : LVDSTS
bits : 8 - 8 (1 bit)
access : read-only
MCLKFAILSTS : MCLKFAILSTS
bits : 9 - 9 (1 bit)
access : read-only
WDTINTSTS : WDTINTSTS
bits : 10 - 10 (1 bit)
access : read-only
OVPSTS : OVPSTS
bits : 11 - 11 (1 bit)
access : read-only
PROTSTS : PROTSTS
bits : 12 - 12 (1 bit)
access : read-only
ACODE : 0xA32C to write
bits : 16 - 31 (16 bit)
Clock Output Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKODIV : clock output divider value
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : clock output enable
bits : 4 - 4 (1 bit)
access : read-write
VDC Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDCWDLY : VDC warm up delay count
bits : 0 - 3 (4 bit)
access : write-only
VDCDE : VDCWDLY value write enable. Write only with VDCWDLY value
bits : 8 - 8 (1 bit)
access : write-only
STOPSEL : VDC STOP MODE Select bit
bits : 25 - 25 (1 bit)
access : write-only
VDCME : VDCMODE value write enable. Write only with VDCMODE value
bits : 31 - 31 (1 bit)
access : write-only
LVD Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDEN : LVDEN
bits : 0 - 0 (1 bit)
access : read-write
LVDLVL : LVDLVL
bits : 1 - 1 (1 bit)
access : read-only
LVDSEL : LVDSEL
bits : 8 - 9 (2 bit)
access : read-write
SELEN : SELEN
bits : 15 - 15 (1 bit)
access : write-only
High Speed Internal OSC Trim Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Reference clock select for self-calibration
bits : 30 - 30 (1 bit)
access : read-write
BISCON : Build in self calibration function enable
bits : 31 - 31 (1 bit)
access : read-write
Build in self calibration control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_COMP : XTAL_COMP
bits : 0 - 15 (16 bit)
access : read-write
INTOSC_COMP : INTOSC_COMP
bits : 16 - 31 (16 bit)
access : write-only
System Reset Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Internal soft reset activation
bits : 0 - 0 (1 bit)
STBOP : STBOP pin output polarity select bit
bits : 4 - 4 (1 bit)
External Main Oscillator Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVCLKEN : Control External Main Oscillator CLK invert
bits : 0 - 0 (1 bit)
access : read-write
INVCLKWEN : Write enable of bit field FILSKIPEN
bits : 7 - 7 (1 bit)
access : write-only
FILSKIPEN : Control External Main Oscillator Filter Skip
bits : 8 - 8 (1 bit)
access : read-write
FILSKIPWEN : Write enable of bit field FILSKIPEN
bits : 15 - 15 (1 bit)
access : write-only
External Mode Status Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOOT : boot pin level
bits : 0 - 0 (1 bit)
Miscellaneous Clock Control Register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCDIV : systick divider
bits : 0 - 7 (8 bit)
access : read-write
STCSEL : systick clock source sel
bits : 8 - 10 (3 bit)
access : read-write
Miscellaneous Clock Control Register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMDIV : MPWM clock n divider
bits : 0 - 7 (8 bit)
PWMCSEL : MPWM Clock source sel
bits : 8 - 10 (3 bit)
Miscellaneous Clock Control Register 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTDIV : WDT divider
bits : 0 - 7 (8 bit)
WDTCSEL : WDT clock sel
bits : 8 - 10 (3 bit)
TIMERDIV : Timer Clock divider
bits : 16 - 23 (8 bit)
TIMERCSEL : Timer Clock source sel
bits : 24 - 26 (3 bit)
Debounce Clock Control Register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDIV : PORT A Debounce Clock N divider
bits : 0 - 7 (8 bit)
PADCSEL : Debounce Clock for Port A source select
bits : 8 - 10 (3 bit)
PBDDIV : PORT B Debounce Clock N divider
bits : 16 - 23 (8 bit)
PBDCSEL : Debounce Clock for Port B source select
bits : 24 - 26 (3 bit)
Debounce Clock Control Register 2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCDDIV : PORT C debounce divider
bits : 0 - 7 (8 bit)
PCDCSEL : debouce clock for port C source clock sel
bits : 8 - 10 (3 bit)
PDDDIV : PORT D debounce divider
bits : 16 - 23 (8 bit)
PDDCSEL : debouce clock for port D source clock sel
bits : 24 - 26 (3 bit)
Miscellaneous Clock Control Register 4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTCDIV : UART Clock N divider
bits : 0 - 7 (8 bit)
UARTCSEL : UART clock source select bit
bits : 8 - 10 (3 bit)
ADCCDIV : ADC Clock N divider
bits : 16 - 23 (8 bit)
ADCCSEL : ADC clock source select bit
bits : 24 - 26 (3 bit)
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