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SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WUER

WUSR

RSER

RSSR

PRER1

PRER2

PER1

PER2

PCER1

PCER2

SMR

CSCR

SCCR

CMR

NMIR

COR

VDCCON

LVDCON

HSIOSCTRIM

BISCCON

SRCR

EMOSCR

EMODR

MCCR1

MCCR2

MCCR3

DBCLK1

DBCLK2

MCCR4


WUER

Wakeup Source Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUER WUER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDWUE WDTWUE FRTWUE GPIOAWUE GPIOBWUE GPIOCWUE GPIODWUE

LVDWUE : LVDWUE
bits : 0 - 0 (1 bit)

WDTWUE : WDTWUE
bits : 1 - 1 (1 bit)

FRTWUE : FRTWUE
bits : 2 - 2 (1 bit)

GPIOAWUE : GPIOAWUE
bits : 8 - 8 (1 bit)

GPIOBWUE : GPIOBWUE
bits : 9 - 9 (1 bit)

GPIOCWUE : GPIOCWUE
bits : 10 - 10 (1 bit)

GPIODWUE : GPIODWUE
bits : 11 - 11 (1 bit)


WUSR

Wakeup Source Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WUSR WUSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDWU WDTWU FRTWU GPIOAWU GPIOBWU GPIOCWU GPIODWU

LVDWU : LVDWU
bits : 0 - 0 (1 bit)

WDTWU : WDTWU
bits : 1 - 1 (1 bit)

FRTWU : FRTWU
bits : 2 - 2 (1 bit)

GPIOAWU : GPIOAWU
bits : 8 - 8 (1 bit)

GPIOBWU : GPIOBWU
bits : 9 - 9 (1 bit)

GPIOCWU : GPIOCWU
bits : 10 - 10 (1 bit)

GPIODWU : GPIODWU
bits : 11 - 11 (1 bit)


RSER

Reset Source Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSER RSER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRST MOFRST MCKFRST WDTRST SWRST CPURST PINRST LOCKUPRST

LVDRST : LVD reset enable
bits : 0 - 0 (1 bit)

MOFRST : MOSC Clock fail reset enable
bits : 1 - 1 (1 bit)

MCKFRST : MCLK Clock fail reset enable
bits : 2 - 2 (1 bit)

WDTRST : watch dog reset enable
bits : 3 - 3 (1 bit)

SWRST : software reset enable
bits : 4 - 4 (1 bit)

CPURST : CPU request reset enable
bits : 5 - 5 (1 bit)

PINRST : external pin reset enable
bits : 6 - 6 (1 bit)

LOCKUPRST : CPU Lock up reset enable bit
bits : 7 - 7 (1 bit)


RSSR

Reset Source Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSSR RSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRST MOFRST MCKFRST WDTRST SWRST CPURST PINRST PORST LOCKUPRST

LVDRST : lvd reset status
bits : 0 - 0 (1 bit)

MOFRST : MOSC Clock fail reset status
bits : 1 - 1 (1 bit)

MCKFRST : MCLK failed reset status
bits : 2 - 2 (1 bit)

WDTRST : watchdog timer reset status
bits : 3 - 3 (1 bit)

SWRST : software reset status
bits : 4 - 4 (1 bit)

CPURST : cpu request reset status
bits : 5 - 5 (1 bit)

PINRST : extenral pin reset status
bits : 6 - 6 (1 bit)

PORST : power on reset status
bits : 7 - 7 (1 bit)

LOCKUPRST : CPU Lock up reset status
bits : 8 - 8 (1 bit)


PRER1

Peripheral Reset Enable Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRER1 PRER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCU FMC WDT PCU DIV64 GPIOA GPIOB GPIOC GPIOD TIMER0 TIMER1 TIMER2 TIMER3 FRT

SCU : Power Management Unit Reset enable
bits : 0 - 0 (1 bit)

FMC : Flash Memory controller Reset enable
bits : 1 - 1 (1 bit)

WDT : WatchDog timer reset enable
bits : 2 - 2 (1 bit)

PCU : Port Controller unit reset enable
bits : 3 - 3 (1 bit)

DIV64 : DIV64 Reset enable
bits : 5 - 5 (1 bit)

GPIOA : GPIOA Reset enable
bits : 8 - 8 (1 bit)

GPIOB : GPIOB Reset enable
bits : 9 - 9 (1 bit)

GPIOC : GPIOC Reset enable
bits : 10 - 10 (1 bit)

GPIOD : GPIOD Reset enable
bits : 11 - 11 (1 bit)

TIMER0 : TIMER0 Reset enable
bits : 16 - 16 (1 bit)

TIMER1 : TIMER1 reset enable
bits : 17 - 17 (1 bit)

TIMER2 : TIMER2 Reset enable
bits : 18 - 18 (1 bit)

TIMER3 : TIMER3 Reset enable
bits : 19 - 19 (1 bit)

FRT : FRT Reset enable
bits : 26 - 26 (1 bit)


PRER2

Peripheral Reset Enable Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRER2 PRER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI I2C UART0 UART1 MPWM ADC

SPI : SPI Reset enable
bits : 0 - 0 (1 bit)

I2C : I2C Reset enable
bits : 4 - 4 (1 bit)

UART0 : UART0 Reset enable
bits : 8 - 8 (1 bit)

UART1 : UART1 Reset enable
bits : 9 - 9 (1 bit)

MPWM : MPWM Reset enable
bits : 16 - 16 (1 bit)

ADC : ADC Reset enable
bits : 20 - 20 (1 bit)


PER1

Peripheral Enable Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER1 PER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV64 GPIOA GPIOB GPIOC GPIOD TIMER0 TIMER1 TIMER2 TIMER3 FRT

DIV64 : DIV64
bits : 5 - 5 (1 bit)

GPIOA : GPIOA
bits : 8 - 8 (1 bit)

GPIOB : GPIOB
bits : 9 - 9 (1 bit)

GPIOC : GPIOC
bits : 10 - 10 (1 bit)

GPIOD : GPIOD
bits : 11 - 11 (1 bit)

TIMER0 : TIMER0
bits : 16 - 16 (1 bit)

TIMER1 : TIMER1
bits : 17 - 17 (1 bit)

TIMER2 : TIMER2
bits : 18 - 18 (1 bit)

TIMER3 : TIMER3
bits : 19 - 19 (1 bit)

FRT : FRT
bits : 26 - 26 (1 bit)


PER2

Peripheral Enable Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER2 PER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI I2C UART0 UART1 MPWM ADC

SPI : SPI Enable
bits : 0 - 0 (1 bit)

I2C : I2C
bits : 4 - 4 (1 bit)

UART0 : UART0
bits : 8 - 8 (1 bit)

UART1 : UART1
bits : 9 - 9 (1 bit)

MPWM : MPWM
bits : 16 - 16 (1 bit)

ADC : ADC
bits : 20 - 20 (1 bit)


PCER1

Peripheral Clock Enable Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCER1 PCER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV64 GPIOA GPIOB GPIOC GPIOD TIMER0 TIMER1 TIMER2 TIMER3 FRT

DIV64 : DIV64
bits : 5 - 5 (1 bit)

GPIOA : GPIOA clock enable
bits : 8 - 8 (1 bit)

GPIOB : GPIOB clock enable
bits : 9 - 9 (1 bit)

GPIOC : GPIOC clock enable
bits : 10 - 10 (1 bit)

GPIOD : GPIOD clock enable
bits : 11 - 11 (1 bit)

TIMER0 : TIMER0
bits : 16 - 16 (1 bit)

TIMER1 : TIMER1 clock enable
bits : 17 - 17 (1 bit)

TIMER2 : TIMER2 clock enable
bits : 18 - 18 (1 bit)

TIMER3 : Timer3 clock enable
bits : 19 - 19 (1 bit)

FRT : FRT clock enable
bits : 26 - 26 (1 bit)


PCER2

Peripheral Clock Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCER2 PCER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI I2C UART0 UART1 MPWM ADC

SPI : SPI clock enable
bits : 0 - 0 (1 bit)

I2C : I2C clock enable
bits : 4 - 4 (1 bit)

UART0 : UART0
bits : 8 - 8 (1 bit)

UART1 : UART1 clock enable
bits : 9 - 9 (1 bit)

MPWM : MPWM clock enable
bits : 16 - 16 (1 bit)

ADC : ADC clock enable
bits : 20 - 20 (1 bit)


SMR

System Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREVMODE VDCAON LSIAON

PREVMODE : PREVMODE
bits : 4 - 5 (2 bit)
access : read-only

VDCAON : VDCAON
bits : 8 - 8 (1 bit)

LSIAON : LSIAON
bits : 9 - 9 (1 bit)


CSCR

Clock Source Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCR CSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCCON HSICON LSICON SOSCCON

MOSCCON : External crystal main oscillator control
bits : 0 - 1 (2 bit)

HSICON : High speed internal oscillator control
bits : 2 - 3 (2 bit)

LSICON : Low speed internal oscillator control
bits : 4 - 5 (2 bit)

SOSCCON : External crystal sub oscillator control
bits : 6 - 7 (2 bit)


SCCR

System Clock Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCR SCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCLKSEL

MCLKSEL : System clock select
bits : 0 - 2 (3 bit)


CMR

Clock Monitoring Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR CMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCSTS MOSCFAIL MOSCIE MOSCMNT MCLKSTS MCLKFAIL MCLKIE MCLKMNT SOSCSTS SOSCFAIL SOSCIE SOSCMNT MCLKREC

MOSCSTS : external OSC status
bits : 0 - 0 (1 bit)
access : read-write

MOSCFAIL : external OSC failed flag
bits : 1 - 1 (1 bit)
access : read-write

MOSCIE : external OSC failed interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

MOSCMNT : External OSC monitor enable
bits : 3 - 3 (1 bit)
access : read-write

MCLKSTS : MCLK clock status
bits : 4 - 4 (1 bit)
access : read-write

MCLKFAIL : MCLK Failed flag
bits : 5 - 5 (1 bit)
access : read-write

MCLKIE : MCLK fail Interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

MCLKMNT : MCLK monitor enable
bits : 7 - 7 (1 bit)
access : read-write

SOSCSTS : Sub Oscillator clock status
bits : 8 - 8 (1 bit)
access : read-write

SOSCFAIL : Sub Oscillator fail interrupt flag
bits : 9 - 9 (1 bit)
access : read-write

SOSCIE : Sub Oscillator fail interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

SOSCMNT : Sub Oscillator monitoring enable
bits : 11 - 11 (1 bit)
access : read-write

MCLKREC : MCLK failed auto recovery
bits : 15 - 15 (1 bit)
access : read-write


NMIR

NMI Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMIR NMIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDEN MCLKFAILEN WDTINTEN OVPEN PROTEN LVDSTS MCLKFAILSTS WDTINTSTS OVPSTS PROTSTS ACODE

LVDEN : LVDEN
bits : 0 - 0 (1 bit)

MCLKFAILEN : MCLKFAILEN
bits : 1 - 1 (1 bit)

WDTINTEN : WDTINTEN
bits : 2 - 2 (1 bit)

OVPEN : OVPEN
bits : 3 - 3 (1 bit)

PROTEN : PROTEN
bits : 4 - 4 (1 bit)

LVDSTS : LVDSTS
bits : 8 - 8 (1 bit)
access : read-only

MCLKFAILSTS : MCLKFAILSTS
bits : 9 - 9 (1 bit)
access : read-only

WDTINTSTS : WDTINTSTS
bits : 10 - 10 (1 bit)
access : read-only

OVPSTS : OVPSTS
bits : 11 - 11 (1 bit)
access : read-only

PROTSTS : PROTSTS
bits : 12 - 12 (1 bit)
access : read-only

ACODE : 0xA32C to write
bits : 16 - 31 (16 bit)


COR

Clock Output Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COR COR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKODIV CLKOEN

CLKODIV : clock output divider value
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : clock output enable
bits : 4 - 4 (1 bit)
access : read-write


VDCCON

VDC Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDCCON VDCCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDCWDLY VDCDE STOPSEL VDCME

VDCWDLY : VDC warm up delay count
bits : 0 - 3 (4 bit)
access : write-only

VDCDE : VDCWDLY value write enable. Write only with VDCWDLY value
bits : 8 - 8 (1 bit)
access : write-only

STOPSEL : VDC STOP MODE Select bit
bits : 25 - 25 (1 bit)
access : write-only

VDCME : VDCMODE value write enable. Write only with VDCMODE value
bits : 31 - 31 (1 bit)
access : write-only


LVDCON

LVD Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVDCON LVDCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDEN LVDLVL LVDSEL SELEN

LVDEN : LVDEN
bits : 0 - 0 (1 bit)
access : read-write

LVDLVL : LVDLVL
bits : 1 - 1 (1 bit)
access : read-only

LVDSEL : LVDSEL
bits : 8 - 9 (2 bit)
access : read-write

SELEN : SELEN
bits : 15 - 15 (1 bit)
access : write-only


HSIOSCTRIM

High Speed Internal OSC Trim Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSIOSCTRIM HSIOSCTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL BISCON

REFSEL : Reference clock select for self-calibration
bits : 30 - 30 (1 bit)
access : read-write

BISCON : Build in self calibration function enable
bits : 31 - 31 (1 bit)
access : read-write


BISCCON

Build in self calibration control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BISCCON BISCCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_COMP INTOSC_COMP

XTAL_COMP : XTAL_COMP
bits : 0 - 15 (16 bit)
access : read-write

INTOSC_COMP : INTOSC_COMP
bits : 16 - 31 (16 bit)
access : write-only


SRCR

System Reset Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCR SRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST STBOP

SWRST : Internal soft reset activation
bits : 0 - 0 (1 bit)

STBOP : STBOP pin output polarity select bit
bits : 4 - 4 (1 bit)


EMOSCR

External Main Oscillator Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMOSCR EMOSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVCLKEN INVCLKWEN FILSKIPEN FILSKIPWEN

INVCLKEN : Control External Main Oscillator CLK invert
bits : 0 - 0 (1 bit)
access : read-write

INVCLKWEN : Write enable of bit field FILSKIPEN
bits : 7 - 7 (1 bit)
access : write-only

FILSKIPEN : Control External Main Oscillator Filter Skip
bits : 8 - 8 (1 bit)
access : read-write

FILSKIPWEN : Write enable of bit field FILSKIPEN
bits : 15 - 15 (1 bit)
access : write-only


EMODR

External Mode Status Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EMODR EMODR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOT

BOOT : boot pin level
bits : 0 - 0 (1 bit)


MCCR1

Miscellaneous Clock Control Register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR1 MCCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCDIV STCSEL

STCDIV : systick divider
bits : 0 - 7 (8 bit)
access : read-write

STCSEL : systick clock source sel
bits : 8 - 10 (3 bit)
access : read-write


MCCR2

Miscellaneous Clock Control Register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR2 MCCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMDIV PWMCSEL

PWMDIV : MPWM clock n divider
bits : 0 - 7 (8 bit)

PWMCSEL : MPWM Clock source sel
bits : 8 - 10 (3 bit)


MCCR3

Miscellaneous Clock Control Register 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR3 MCCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTDIV WDTCSEL TIMERDIV TIMERCSEL

WDTDIV : WDT divider
bits : 0 - 7 (8 bit)

WDTCSEL : WDT clock sel
bits : 8 - 10 (3 bit)

TIMERDIV : Timer Clock divider
bits : 16 - 23 (8 bit)

TIMERCSEL : Timer Clock source sel
bits : 24 - 26 (3 bit)


DBCLK1

Debounce Clock Control Register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLK1 DBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDIV PADCSEL PBDDIV PBDCSEL

PADDIV : PORT A Debounce Clock N divider
bits : 0 - 7 (8 bit)

PADCSEL : Debounce Clock for Port A source select
bits : 8 - 10 (3 bit)

PBDDIV : PORT B Debounce Clock N divider
bits : 16 - 23 (8 bit)

PBDCSEL : Debounce Clock for Port B source select
bits : 24 - 26 (3 bit)


DBCLK2

Debounce Clock Control Register 2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLK2 DBCLK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCDDIV PCDCSEL PDDDIV PDDCSEL

PCDDIV : PORT C debounce divider
bits : 0 - 7 (8 bit)

PCDCSEL : debouce clock for port C source clock sel
bits : 8 - 10 (3 bit)

PDDDIV : PORT D debounce divider
bits : 16 - 23 (8 bit)

PDDCSEL : debouce clock for port D source clock sel
bits : 24 - 26 (3 bit)


MCCR4

Miscellaneous Clock Control Register 4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCR4 MCCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UARTCDIV UARTCSEL ADCCDIV ADCCSEL

UARTCDIV : UART Clock N divider
bits : 0 - 7 (8 bit)

UARTCSEL : UART clock source select bit
bits : 8 - 10 (3 bit)

ADCCDIV : ADC Clock N divider
bits : 16 - 23 (8 bit)

ADCCSEL : ADC clock source select bit
bits : 24 - 26 (3 bit)



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