\n

FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DR

TMR

DIRTY

TICK

CRC

CFG

MR

HWID

BOOTCR

WPROT

RPROT

CR

AR


DR

Flash Memory Data Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATA

FDATA : Flash PGM data
bits : 0 - 31 (32 bit)


TMR

Flash Memory Timer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR TMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR

TMR : Erase/PGM timer
bits : 0 - 17 (18 bit)


DIRTY

Flash Memory Dirty Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRTY DIRTY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDIRTY

FDIRTY : Write any value to clear the Cache line fill
bits : 0 - 31 (32 bit)


TICK

Flash Memory Tick Timer register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TICK TICK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTICK

FTICK : TICK
bits : 0 - 31 (32 bit)


CRC

Flash Memory CRC value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC CRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC

CRC : CRC16 Value
bits : 0 - 15 (16 bit)


CFG

Flash Memory CONFIG value register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCEN CRCINIT WAIT TESTCLK HRESPD WRITEKEY

CRCEN : CRC16 Enable
bits : 6 - 6 (1 bit)

CRCINIT : CRCINIT
bits : 7 - 7 (1 bit)

WAIT : WAIT
bits : 8 - 9 (2 bit)

TESTCLK : TESTCLK
bits : 12 - 12 (1 bit)

HRESPD : HRESPD
bits : 15 - 15 (1 bit)

WRITEKEY : WRITEKEY
bits : 16 - 31 (16 bit)


MR

Flash Memory Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACODE FMOD FEMOD TRM TRMEN PROTEN AMBAEN TESTEN IDLE

ACODE : Flash Mode/Trim Mode
bits : 0 - 7 (8 bit)
access : read-write

FMOD : Flash Mode status
bits : 8 - 8 (1 bit)
access : read-only

FEMOD : Flash Mode entry status
bits : 9 - 9 (1 bit)
access : read-only

TRM : Trim Mode status
bits : 16 - 16 (1 bit)
access : read-only

TRMEN : Trim Mode entry status
bits : 17 - 17 (1 bit)
access : read-only

PROTEN : Flash protection
bits : 21 - 21 (1 bit)
access : read-only

AMBAEN : AMBA mode enable
bits : 22 - 22 (1 bit)
access : read-only

TESTEN : Flash test
bits : 23 - 23 (1 bit)
access : read-only

IDLE : Idle mode status
bits : 24 - 24 (1 bit)
access : read-only


HWID

Flash Hardware ID Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWID HWID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FHWID

FHWID : FHWID Value
bits : 0 - 31 (32 bit)


BOOTCR

Boot ROM Remap Clear Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOTCR BOOTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOTROM SREMAP

BOOTROM : Boot mode
bits : 0 - 0 (1 bit)

SREMAP : SRAM remap enable
bits : 4 - 4 (1 bit)


WPROT

Flash Memory Write Protection Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPROT WPROT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP WPEN

WP : Sector protect
bits : 0 - 15 (16 bit)

WPEN : WP access enable
bits : 24 - 31 (8 bit)


RPROT

Flash Memory Read Protection Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPROT RPROT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPEN JTAGDIS LOCK1 LOCK2

RPEN : Read Protection Enable
bits : 0 - 7 (8 bit)
access : read-write

JTAGDIS : JTAG Disable State Flag
bits : 29 - 29 (1 bit)
access : read-only

LOCK1 : Read Protection Level 1 State Flag
bits : 30 - 30 (1 bit)
access : read-only

LOCK2 : Read Protection Level 2 State Flag
bits : 31 - 31 (1 bit)
access : read-only


CR

Flash Memory Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBR ERS PGM PBLD WE PMODE PPGM SUBACT AEF AEE OTPE DMYE BLKE PVER EVER VPPOUT TEST TMREN OTP0 OTP1 OTP2 OTP3

PBR : page buffer reset
bits : 0 - 0 (1 bit)

ERS : program mode/erase mode Enable
bits : 1 - 1 (1 bit)

PGM : PGM
bits : 2 - 2 (1 bit)

PBLD : page buffer load
bits : 3 - 3 (1 bit)

WE : write Enable
bits : 4 - 4 (1 bit)

PMODE : Pmode Enable
bits : 5 - 5 (1 bit)

PPGM : PPGM
bits : 6 - 6 (1 bit)

SUBACT : SUBACT
bits : 7 - 7 (1 bit)

AEF : All Erase
bits : 8 - 8 (1 bit)

AEE : AEE
bits : 9 - 9 (1 bit)

OTPE : OTP area a,b,c,d enable
bits : 10 - 10 (1 bit)

DMYE : DUMMY Area enable
bits : 11 - 11 (1 bit)

BLKE : 128page write enable for full chip writing to save program time
bits : 12 - 12 (1 bit)

PVER : Program verify mode
bits : 13 - 13 (1 bit)

EVER : Erase verify Mode
bits : 14 - 14 (1 bit)

VPPOUT : Charge pump Vpp Output
bits : 15 - 15 (1 bit)

TEST : TEST
bits : 16 - 17 (2 bit)

TMREN : program timer enable
bits : 20 - 20 (1 bit)
access : read-write

OTP0 : OTP0
bits : 28 - 28 (1 bit)

OTP1 : OTP1
bits : 29 - 29 (1 bit)

OTP2 : OTP2
bits : 30 - 30 (1 bit)

OTP3 : OTP3
bits : 31 - 31 (1 bit)


AR

Flash Memory Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADDR

FADDR : 16K words address
bits : 0 - 14 (15 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.