\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : recevied/transmit data
bits : 0 - 7 (8 bit)
Transmit Data Hold Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
THR : received/transmit data
bits : 0 - 7 (8 bit)
UART Data Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXINV : TX Data Inversion selection
bits : 2 - 2 (1 bit)
RXINV : Rx Data Inversion selection
bits : 3 - 3 (1 bit)
LBON : Local loopback test mode enable
bits : 4 - 4 (1 bit)
UART Line Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data recevied
bits : 0 - 0 (1 bit)
OE : overrun error
bits : 1 - 1 (1 bit)
PE : parity error
bits : 2 - 2 (1 bit)
FE : frame error
bits : 3 - 3 (1 bit)
BI : break condition indication bit
bits : 4 - 4 (1 bit)
THRE : Transmit holding register empty
bits : 5 - 5 (1 bit)
TEMT : Transmit empty
bits : 6 - 6 (1 bit)
Baud rate Divisor Latch Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BDR : baudrate setting
bits : 0 - 15 (16 bit)
Baud rate Fraction Counter Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFR : Fraction counter value
bits : 0 - 7 (8 bit)
Inter-frame Delay Time Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITVAL : wait time is decied by this value
bits : 0 - 2 (3 bit)
DMS : Data Bit Multi sampling enable
bits : 6 - 6 (1 bit)
SMS : Start Bit Multi sampling enable
bits : 7 - 7 (1 bit)
UART Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIE : Data receive interrupt enable
bits : 0 - 0 (1 bit)
THREIE : Transmit holding register empty interrupt enable
bits : 1 - 1 (1 bit)
RLSIE : receiver line status interrupt enable
bits : 2 - 2 (1 bit)
UART Interrupt ID Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPEN : Interrupt pending bit
bits : 0 - 0 (1 bit)
access : read-only
IID : Interrupt source ID
bits : 1 - 3 (3 bit)
access : read-only
TXE : Interrupt source ID
bits : 4 - 4 (1 bit)
access : read-only
DR : Data Receive Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only
THRE : Transmit Holding register empty flag
bits : 17 - 17 (1 bit)
access : read-only
RLS : Receiver line status flag
bits : 18 - 18 (1 bit)
access : read-only
UART Line Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLEN : Data length in one transfer word
bits : 0 - 1 (2 bit)
STOPBIT : STOPBIT
bits : 2 - 2 (1 bit)
PEN : parity bit transfer enable
bits : 3 - 3 (1 bit)
PARITY : PARITY
bits : 4 - 4 (1 bit)
STICKP : STICK
bits : 5 - 5 (1 bit)
BREAK : BREAK
bits : 6 - 6 (1 bit)
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