\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
SPI n Receive Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Data
bits : 0 - 16 (17 bit)
SPI n Transmit Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Data
bits : 0 - 16 (17 bit)
SPI n Enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SPI ENABLE bit
bits : 0 - 0 (1 bit)
SPI n delay Length Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STL : Start delay length
bits : 0 - 7 (8 bit)
BTL : Burst delay length
bits : 8 - 15 (8 bit)
SPL : Stop delay length
bits : 16 - 23 (8 bit)
SPI n Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITSZ : Transmit/receive Data bits select bit
bits : 0 - 1 (2 bit)
CPOL : SPI clock polarity bit
bits : 2 - 2 (1 bit)
CPHA : SPI clock phase bit
bits : 3 - 3 (1 bit)
MSBF : MSB/LSB transmit select bit
bits : 4 - 4 (1 bit)
MS : master/slaver select bit
bits : 5 - 5 (1 bit)
SSPOL : SS Signal polarity select bit
bits : 8 - 8 (1 bit)
SSMO : SS output signal select bit
bits : 9 - 9 (1 bit)
SSMASK : SS Signal masking bit in slave mode
bits : 10 - 10 (1 bit)
LBE : Loop-back mode select bit in master mode
bits : 11 - 11 (1 bit)
SSOUT : SS output signal select bit
bits : 12 - 12 (1 bit)
SSMOD : SS Auto/Manual Output select bit
bits : 13 - 13 (1 bit)
RXIE : Receive interrupt enable bit
bits : 14 - 14 (1 bit)
TXIE : Transmit interrupt enable bit
bits : 15 - 15 (1 bit)
SSCIE : SSn Edge Change Interrupt enable bit
bits : 16 - 16 (1 bit)
RXBC : Rx buffer clear bit
bits : 19 - 19 (1 bit)
TXBC : Tx buffer clear bit
bits : 20 - 20 (1 bit)
SPI n Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRDY : receive buffer ready flag
bits : 0 - 0 (1 bit)
access : read-only
TRDY : Transmit buffer empty flag
bits : 1 - 1 (1 bit)
access : read-only
TXIDLE : transmit/receive operation flag
bits : 2 - 2 (1 bit)
access : read-only
UDRF : transmit underrun error flag
bits : 3 - 3 (1 bit)
access : read-write
OVRF : receive overrun error flag
bits : 4 - 4 (1 bit)
access : read-write
SSON : SS signal status flag
bits : 5 - 5 (1 bit)
access : read-write
SSDET : The rising edge of SS detect flag
bits : 6 - 6 (1 bit)
access : read-write
SPI n Baud Rate Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR : buadrate
bits : 0 - 15 (16 bit)
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