\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Divider Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Divide operation start command.
bits : 0 - 0 (1 bit)
MODE : Start operation mode
bits : 4 - 4 (1 bit)
DONE : Divider operation done flag
bits : 8 - 8 (1 bit)
BUSY : Divider is now under operating
bits : 9 - 9 (1 bit)
I_ERROR : Divide by zero flag
bits : 10 - 10 (1 bit)
QREG (Quotient) Low 32bit Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QREG (Quotient) High 32bit Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RREG (Remainter) Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AREGL (Dividend) Low 32bit Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AREG (Dividend) High 32bit Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BREG (Divisor) Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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