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address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
ADC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : TRGSEL
bits : 0 - 1 (2 bit)
ADMOD : ADC convert mode
bits : 4 - 5 (2 bit)
ARST : ARST
bits : 6 - 6 (1 bit)
ADEN : ADC Enable
bits : 7 - 7 (1 bit)
SEQCNT : SEQCNT
bits : 8 - 10 (3 bit)
STSEL : STSEL
bits : 12 - 16 (5 bit)
ADC Sequence Channel Selection Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQ0CH : 1st conversion sequence channel selection
bits : 0 - 3 (4 bit)
SEQ1CH : 2nd conversion sequence channel selection
bits : 4 - 7 (4 bit)
SEQ2CH : 3rd conversion sequence channel selection
bits : 8 - 11 (4 bit)
SEQ3CH : 4th conversion sequence channel selection
bits : 12 - 15 (4 bit)
SEQ4CH : 5th conversion sequence channel selection
bits : 16 - 19 (4 bit)
SEQ5CH : 6th conversion sequence channel selection
bits : 20 - 23 (4 bit)
SEQ6CH : 7th conversion sequence channel selection
bits : 24 - 27 (4 bit)
SEQ7CH : 8th conversion sequence channel selection
bits : 28 - 31 (4 bit)
ADCn Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASTART : ADC conversion start
bits : 0 - 0 (1 bit)
access : read-write
ASTOP : ADC Stop
bits : 7 - 7 (1 bit)
access : write-only
ADCn Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCIRQ : EOCIRQ
bits : 0 - 0 (1 bit)
EOSIRQ : EOSIRQ
bits : 2 - 2 (1 bit)
TRGIRQ : ADC Trigger interrupt flag
bits : 3 - 3 (1 bit)
ABUSY : ADC conversion busy flag
bits : 6 - 6 (1 bit)
EOC : ADC End Flag
bits : 7 - 7 (1 bit)
Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCIRQE : ADC single conversion interrupt enable
bits : 0 - 0 (1 bit)
EOSIRQE : ADC sequence conversion interrupt enable
bits : 2 - 2 (1 bit)
TRGIRQE : ADC trigger conversion interrupt enable
bits : 3 - 3 (1 bit)
ADC Data Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Data Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Data Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Data Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
Current Sequence/Channel Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACH : Current Active Channel
bits : 0 - 3 (4 bit)
CSEQN : CSEQN
bits : 4 - 6 (3 bit)
ADC Data Register 4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Data Register 5
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Data Register 6
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Data Register 7
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC conversion result data
bits : 4 - 15 (12 bit)
Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKINVT : divided clock inversion
bits : 5 - 5 (1 bit)
EXTCLK : ADCuse external clock
bits : 6 - 6 (1 bit)
ADCPD : ADC Power down
bits : 7 - 7 (1 bit)
CLKDIV : ADC clock divider
bits : 8 - 14 (7 bit)
ADCPDA : ADC R-ADC disable to save power
bits : 15 - 15 (1 bit)
ADC Trigger Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQTRG0 : 1st Sequence Trigger Source
bits : 0 - 3 (4 bit)
SEQTRG1 : 2nd Sequence Trigger Source
bits : 4 - 7 (4 bit)
SEQTRG2 : 3rd Sequence Trigger Source
bits : 8 - 11 (4 bit)
SEQTRG3 : 4th Sequence Trigger Source
bits : 12 - 15 (4 bit)
SEQTRG4 : 5th Sequence Trigger Source
bits : 16 - 19 (4 bit)
SEQTRG5 : 6th Sequence Trigger Source
bits : 20 - 23 (4 bit)
SEQTRG6 : 7th Sequence Trigger Source
bits : 24 - 27 (4 bit)
SEQTRG7 : 8th Sequence Trigger Source
bits : 28 - 31 (4 bit)
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