\n

TGECR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR


CR

Timer Group Encoder Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QDMOD QDPHSWAP QDPHZEG QDPHAEG QDPHBEG ADIRCON BDIRCON PDIRCON RDIRCON

QDMOD : Quadrature decoder mode
bits : 0 - 0 (1 bit)

QDPHSWAP : Quadrature mode phase Z count for Revolution
bits : 2 - 2 (1 bit)

QDPHZEG : Quadrature mode phase Z count for Revolution
bits : 3 - 3 (1 bit)

QDPHAEG : Quadrature mode phase A count for position count
bits : 4 - 5 (2 bit)

QDPHBEG : Quadrature mode phase B count for position count
bits : 6 - 7 (2 bit)

ADIRCON : PHASE A counter direction control
bits : 8 - 8 (1 bit)

BDIRCON : Phase B counter direction control
bits : 9 - 9 (1 bit)

PDIRCON : Position counter direction control
bits : 10 - 10 (1 bit)

RDIRCON : Revolution counter direction control
bits : 11 - 11 (1 bit)



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