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MPWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

DUH

DVH

DWH

DUL

DVL

DWL

CR1

CR2

SR

IER

CNT

DTR

PMR

PCR

PSR

OVCR

OVSR

ATCR

ATR1

ATR2

ATR3

ATR4

ATR5

ATR6

OCR

PRD


MR

MPWM Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDOWN PDUP FORCM FORCEN UALL UPDATE MCHMOD MOTOR

UPDOWN : PWM counter mode
bits : 0 - 0 (1 bit)

PDUP : period duty update at ..
bits : 1 - 1 (1 bit)

FORCM : force mode
bits : 4 - 5 (2 bit)

FORCEN : force mode
bits : 7 - 7 (1 bit)

UALL : Update all duty register
bits : 8 - 8 (1 bit)

UPDATE : update
bits : 9 - 9 (1 bit)

MCHMOD : Motor control channel mode
bits : 12 - 13 (2 bit)

MOTOR : Normal/Motor mode
bits : 15 - 15 (1 bit)


DUH

MPWM Duty UH Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUH DUH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of UH output
bits : 0 - 15 (16 bit)


DVH

MPWM Duty VH Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVH DVH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of VH output
bits : 0 - 15 (16 bit)


DWH

MPWM Duty WH Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWH DWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of WH output
bits : 0 - 15 (16 bit)


DUL

MPWM Duty UL Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUL DUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of UL output
bits : 0 - 15 (16 bit)


DVL

MPWM Duty UL Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVL DVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of VL output
bits : 0 - 15 (16 bit)


DWL

MPWM Duty WL Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWL DWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY

DUTY : duty of WL output
bits : 0 - 15 (16 bit)


CR1

MPWM Control Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT PWMEN IRQN IRQMD INTVEN

HALT : PWM HALT
bits : 0 - 0 (1 bit)

PWMEN : PWM enable
bits : 7 - 7 (1 bit)

IRQN : IRQ intervel Number
bits : 8 - 10 (3 bit)

IRQMD : IRQ mode
bits : 12 - 13 (2 bit)

INTVEN : IRQ intervel mode
bits : 15 - 15 (1 bit)


CR2

MPWM Control Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTART

PSTART : PWM start
bits : 0 - 0 (1 bit)


SR

MPWM Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWLIRQ DWHIRQ DVLIRQ DVHIRQ DULIRQ DUHIRQ BOTIRQ PRDIRQ IRQCNT DOWN

DWLIRQ : duty WL interrupt flag
bits : 0 - 0 (1 bit)

DWHIRQ : duty WH interrupt flag
bits : 1 - 1 (1 bit)

DVLIRQ : duty VL interrupt flag
bits : 2 - 2 (1 bit)

DVHIRQ : duty VH interrupt flag
bits : 3 - 3 (1 bit)

DULIRQ : duty UL interrupt flag
bits : 4 - 4 (1 bit)

DUHIRQ : duty UH interrupt flag
bits : 5 - 5 (1 bit)

BOTIRQ : PWM bottom interrupt flag
bits : 6 - 6 (1 bit)

PRDIRQ : PWM period interrupt flag
bits : 7 - 7 (1 bit)

IRQCNT : PWM count number of period match
bits : 12 - 14 (3 bit)

DOWN : PWM count up/down
bits : 15 - 15 (1 bit)


IER

MPWM Interrupt Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWLIEN DWHIEN DVLIEN DVHIEN DULIEN DUHIEN BOTIE PRDIEN

DWLIEN : duty WL interrupt enable
bits : 0 - 0 (1 bit)

DWHIEN : duty WH interrupt enable
bits : 1 - 1 (1 bit)

DVLIEN : duty VL interrupt enable
bits : 2 - 2 (1 bit)

DVHIEN : duty VH interrupt enable
bits : 3 - 3 (1 bit)

DULIEN : duty UL interrupt enable
bits : 4 - 4 (1 bit)

DUHIEN : duty UH interrupt enable
bits : 5 - 5 (1 bit)

BOTIE : bottom interrupt enable
bits : 6 - 6 (1 bit)

PRDIEN : Period interrupt enable
bits : 7 - 7 (1 bit)


CNT

MPWM Counter Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : pwm counter value
bits : 0 - 15 (16 bit)


DTR

MPWM Dead Time Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTR DTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT DTCLK DTEN

DT : dead time value
bits : 0 - 7 (8 bit)

DTCLK : dead time clk select
bits : 8 - 8 (1 bit)

DTEN : dead time Enable
bits : 15 - 15 (1 bit)


PMR

MPWM Port Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMR PMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POLWL POLWH POLVL POLVH POLUL POLUH PMOD

POLWL : Polarity of UL PIN
bits : 0 - 0 (1 bit)

POLWH : Polarity of UH PIN
bits : 1 - 1 (1 bit)

POLVL : Polarity of UL PIN
bits : 2 - 2 (1 bit)

POLVH : Polarity of UH PIN
bits : 3 - 3 (1 bit)

POLUL : Polarity of UL PIN
bits : 4 - 4 (1 bit)

POLUH : Polarity of UH PIN
bits : 5 - 5 (1 bit)

PMOD : PWM pulse mode
bits : 8 - 9 (2 bit)


PCR

MPWM Protection control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR PCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTSEL PTDBC PROTCLR WLPROT WHPROT VLPROT VHPROT ULPROT UHPROT PROTDIS AD0IN AD1IN AD2IN C0IN C1IN C2IN C3IN PRTIN

PTSEL : protection mode sel
bits : 0 - 1 (2 bit)

PTDBC : protection signal debounce
bits : 4 - 6 (3 bit)

PROTCLR : protection clear
bits : 7 - 7 (1 bit)

WLPROT : WL protection output
bits : 8 - 8 (1 bit)

WHPROT : WH protection output
bits : 9 - 9 (1 bit)

VLPROT : VL protection output
bits : 10 - 10 (1 bit)

VHPROT : VH protection output
bits : 11 - 11 (1 bit)

ULPROT : UL protection output
bits : 12 - 12 (1 bit)

UHPROT : UH protection output
bits : 13 - 13 (1 bit)

PROTDIS : Protect mode disable
bits : 15 - 15 (1 bit)

AD0IN : ADC0 Comparator output
bits : 16 - 16 (1 bit)

AD1IN : ADC1 Comparator output
bits : 17 - 17 (1 bit)

AD2IN : ADC2 Comparator output
bits : 18 - 18 (1 bit)

C0IN : comparator 0 output
bits : 19 - 19 (1 bit)

C1IN : comparator 1 output
bits : 20 - 20 (1 bit)

C2IN : comparator 2 output
bits : 21 - 21 (1 bit)

C3IN : comparator 3 output
bits : 22 - 22 (1 bit)

PRTIN : External PRTIN pin input (active high)
bits : 23 - 23 (1 bit)


PSR

MPWM Protection Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTIN PROTEN PROTPAT

PROTIN : Protection Input status
bits : 0 - 0 (1 bit)

PROTEN : Protection mode enable status
bits : 7 - 7 (1 bit)

PROTPAT : lock safety pattern to set or reset protection
bits : 16 - 31 (16 bit)


OVCR

MPWM Over Voltage control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OVCR OVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVSEL OVDBC OVCLR OVEN AD0IN AD1IN AD2IN C0IN C1IN C2IN C3IN OVIN

OVSEL : OV voltage proection mode select
bits : 0 - 1 (2 bit)

OVDBC : OV voltage protection signal debounce
bits : 4 - 6 (3 bit)

OVCLR : OV protection clear
bits : 7 - 7 (1 bit)

OVEN : over voltage protection mode
bits : 15 - 15 (1 bit)

AD0IN : ADC0 Comparator output
bits : 16 - 16 (1 bit)

AD1IN : ADC1 Comparator output
bits : 17 - 17 (1 bit)

AD2IN : ADC2 Comparator output
bits : 18 - 18 (1 bit)

C0IN : comparator 0 output
bits : 19 - 19 (1 bit)

C1IN : comparator 1 output
bits : 20 - 20 (1 bit)

C2IN : comparator 2 output
bits : 21 - 21 (1 bit)

C3IN : comparator 3 output
bits : 22 - 22 (1 bit)

OVIN : ext OV pin input
bits : 23 - 23 (1 bit)


OVSR

MPWM Over Voltage Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OVSR OVSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVPIN OVSTAT

OVPIN : Over voltage protection input status
bits : 0 - 0 (1 bit)

OVSTAT : Over voltage protection mode status
bits : 7 - 7 (1 bit)


ATCR

MPWM ADC Trigger Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATCR ATCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATRGM ATRGEN ATRGALL

ATRGM : ADC Trigger Mode
bits : 0 - 1 (2 bit)

ATRGEN : ADC Trigger Mode Enable
bits : 7 - 7 (1 bit)

ATRGALL : ADC Trigger register 0 match event
bits : 8 - 8 (1 bit)


ATR1

MPWMn ADC Trigger Counter 1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR1 ATR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR2

MPWMn ADC Trigger Counter 2 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR2 ATR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR3

MPWMn ADC Trigger Counter 3 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR3 ATR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR4

MPWMn ADC Trigger Counter 4 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR4 ATR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR5

MPWMn ADC Trigger Counter 5 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR5 ATR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


ATR6

MPWMn ADC Trigger Counter 6 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATR6 ATR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATCNT ATMOD ATUDT

ATCNT : ADC Trigger counter
bits : 0 - 15 (16 bit)

ATMOD : ADC Trigger mode register
bits : 16 - 17 (2 bit)

ATUDT : Trigger register update mode
bits : 19 - 19 (1 bit)


OCR

MPWM Output Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCR OCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLEN WHVAL VLVAL VHVAL ULVAL UHVAL

WLEN : PWM WL output control in force mode
bits : 0 - 0 (1 bit)

WHVAL : PWM WH output control in force mode
bits : 1 - 1 (1 bit)

VLVAL : PWM VL output control in force mode
bits : 2 - 2 (1 bit)

VHVAL : PWM VH output control in force mode
bits : 3 - 3 (1 bit)

ULVAL : PWM UL output control in force mode
bits : 4 - 4 (1 bit)

UHVAL : PWM UH output control in force mode
bits : 5 - 5 (1 bit)


PRD

MPWM Period Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD PRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : PWM period
bits : 0 - 15 (16 bit)



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