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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

TRG1

TRG2

BCSR

CR2

SR

IER

DDR

CSR

CCR

CR1

TRG0


MR

ADCn Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSRC TRGEN ADCMOD ADCEN BSTCNT BWAITEN DMACH DMAEN BWAIT

TRGSRC : ADC Trigger source sel
bits : 0 - 2 (3 bit)

TRGEN : Trigger sources enable
bits : 3 - 3 (1 bit)

ADCMOD : ADC convert mode
bits : 4 - 5 (2 bit)

ADCEN : ADC Enable
bits : 7 - 7 (1 bit)

BSTCNT : No Burst Mode
bits : 8 - 10 (3 bit)

BWAITEN : Burst wait enable
bits : 12 - 12 (1 bit)

DMACH : DMA channel option
bits : 16 - 16 (1 bit)

DMAEN : DMA enable
bits : 17 - 17 (1 bit)

BWAIT : burst wait count value
bits : 24 - 31 (8 bit)


TRG1

ADC Trigger 1 Channel Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRG1 TRG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP1TRG1 MP1TRG2 MP1TRG3 MP1TRG4 MP1TRG5 MP1TRG6 TRG1EN

MP1TRG1 : ADC channel n select for MPWM1 ADC trigger1 operation
bits : 0 - 3 (4 bit)

MP1TRG2 : ADC channel n select for MPWM1 ADC trigger2 operation
bits : 4 - 7 (4 bit)

MP1TRG3 : ADC channel n select for MPWM1 ADC trigger3 operation
bits : 8 - 11 (4 bit)

MP1TRG4 : ADC channel n select for MPWM1 ADC trigger4 operation
bits : 12 - 15 (4 bit)

MP1TRG5 : ADC channel n select for MPWM1 ADC trigger5 operation
bits : 16 - 19 (4 bit)

MP1TRG6 : ADC channel n select for MPWM1 ADC trigger6 operation
bits : 20 - 23 (4 bit)

TRG1EN : MP1TRGn enable
bits : 24 - 29 (6 bit)


TRG2

ADC Trigger 2 Channel Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRG2 TRG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0CH T1CH EXTCH

T0CH : ADC channel n select for timer0 trigger operation
bits : 0 - 3 (4 bit)

T1CH : ADC channel n select for timer1 trigger operation
bits : 4 - 7 (4 bit)

EXTCH : ADC channel n select for external trigger operation
bits : 8 - 11 (4 bit)


BCSR

ADC Burst Mode Channel select
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCSR BCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BST1CH BST2CH BST3CH BST4CH BST5CH BST6CH BST7CH BST8CH

BST1CH : 1st burst mode coversion channel selection
bits : 0 - 3 (4 bit)

BST2CH : 2nd burst mode coversion channel selection
bits : 4 - 7 (4 bit)

BST3CH : 3rd burst mode coversion channel selection
bits : 8 - 11 (4 bit)

BST4CH : 4th burst mode coversion channel selection
bits : 12 - 15 (4 bit)

BST5CH : 5th burst mode coversion channel selection
bits : 16 - 19 (4 bit)

BST6CH : 6th burst mode coversion channel selection
bits : 20 - 23 (4 bit)

BST7CH : 7th burst mode coversion channel selection
bits : 24 - 27 (4 bit)

BST8CH : 8th burst mode coversion channel selection
bits : 28 - 31 (4 bit)


CR2

ADCn Control Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTART ASTOP

ASTART : ADC conversion start
bits : 0 - 0 (1 bit)
access : read-write

ASTOP : ADC Stop
bits : 4 - 4 (1 bit)
access : write-only


SR

ADCn Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIRQ CIRQ BIRQ TIRQ DMAIRQ DOVRUN ABUSY ADEND BSTAT TRG ADCH MPWM0TRG MPWM1TRG

SIRQ : ADC single interrupt flag
bits : 0 - 0 (1 bit)

CIRQ : ADC continuous interrupt flag
bits : 1 - 1 (1 bit)

BIRQ : ADC burst interrupt flag
bits : 2 - 2 (1 bit)

TIRQ : ADC Trigger interrupt flag
bits : 3 - 3 (1 bit)

DMAIRQ : DMA received/transfer is done
bits : 4 - 4 (1 bit)

DOVRUN : DMA overrun flag
bits : 5 - 5 (1 bit)

ABUSY : ADC conversion busy flag
bits : 6 - 6 (1 bit)

ADEND : ADC End Flag
bits : 7 - 7 (1 bit)

BSTAT : Burst mode operation count status
bits : 8 - 10 (3 bit)

TRG : Trigger event status
bits : 11 - 11 (1 bit)

ADCH : ADC channel bits of present operation
bits : 12 - 15 (4 bit)

MPWM0TRG : MPWM0TRG
bits : 16 - 21 (6 bit)

MPWM1TRG : MPWM1TRG
bits : 24 - 29 (6 bit)


IER

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIEN CIEN BIEN TIEN DIEN

SIEN : ADC single conversion intterupt enable
bits : 0 - 0 (1 bit)

CIEN : ADC continus conversion interrupt enable
bits : 1 - 1 (1 bit)

BIEN : ADC burst conversion interrupt enable
bits : 2 - 2 (1 bit)

TIEN : ADC Trigger conversion intterupt enable
bits : 3 - 3 (1 bit)

DIEN : DMA done interrupt enable
bits : 4 - 4 (1 bit)


DDR

ADC 0/1/2 DMA Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR DDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADMACH ADDMAR

ADMACH : ADC data channel indicator
bits : 0 - 3 (4 bit)

ADDMAR : ADC conversion result data
bits : 4 - 15 (12 bit)


CSR

ADCn Channel Select Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL

CHSEL : channel select
bits : 0 - 3 (4 bit)


CCR

ADC Channel Compare Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVAL CCH LTE COMPOUT

CVAL : compare value
bits : 4 - 15 (12 bit)

CCH : compare channel select
bits : 16 - 19 (4 bit)

LTE : compare direction(greater/less)
bits : 20 - 20 (1 bit)

COMPOUT : ADC compare operation enable
bits : 23 - 23 (1 bit)
access : read-only


CR1

ADCn Control Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STSEL CLKINVT EXTCLK ADCPD CLKDIV ADCPDA

STSEL : Sampling time selection
bits : 0 - 4 (5 bit)

CLKINVT : divided clock inversion
bits : 5 - 5 (1 bit)

EXTCLK : ADCuse external clock
bits : 6 - 6 (1 bit)

ADCPD : ADC Power down
bits : 7 - 7 (1 bit)

CLKDIV : ADC clock divider
bits : 8 - 14 (7 bit)

ADCPDA : ADC R-ADC disable to save power
bits : 15 - 15 (1 bit)


TRG0

ADC Trigger 0 Channel Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRG0 TRG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP0TRG1 MP0TRG2 MP0TRG3 MP0TRG4 MP0TRG5 MP0TRG6 TRG0EN

MP0TRG1 : ADC channel n select for MPWM0 ADC trigger1 operation
bits : 0 - 3 (4 bit)

MP0TRG2 : ADC channel n select for MPWM0 ADC trigger2 operation
bits : 4 - 7 (4 bit)

MP0TRG3 : ADC channel n select for MPWM0 ADC trigger3 operation
bits : 8 - 11 (4 bit)

MP0TRG4 : ADC channel n select for MPWM0 ADC trigger4 operation
bits : 12 - 15 (4 bit)

MP0TRG5 : ADC channel n select for MPWM0 ADC trigger5 operation
bits : 16 - 19 (4 bit)

MP0TRG6 : ADC channel n select for MPWM0 ADC trigger6 operation
bits : 20 - 23 (4 bit)

TRG0EN : MP0TRGn enable
bits : 24 - 29 (6 bit)



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