\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
OPAMP 0 Control Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)
OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)
Comparator 0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)
CINSEL : Comparator input select
bits : 1 - 1 (1 bit)
CMPEN : Comparator enable(0)/disable(1)
bits : 4 - 4 (1 bit)
Comparator 1 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)
CINSEL : Comparator input select
bits : 1 - 1 (1 bit)
CMPEN : Comparator enable
bits : 4 - 4 (1 bit)
Comparator 2 Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)
CINSEL : Comparator input select
bits : 1 - 1 (1 bit)
CMPEN : Comparator enable
bits : 4 - 4 (1 bit)
Comparator 3 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)
CINSEL : Comparator input select
bits : 1 - 1 (1 bit)
CMPEN : Comparator enable
bits : 4 - 4 (1 bit)
Comparator de-bounce Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0DBNC :
bits : 0 - -1 ( bit)
C1DBNC :
bits : 4 - 3 ( bit)
C2DBNC :
bits : 8 - 7 ( bit)
C3DBNC : Debouce shift selection
bits : 12 - 15 (4 bit)
DBNCTB : Debounce time base counter
bits : 16 - 23 (8 bit)
Comparator Interrupt Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0IMOD :
bits : 0 - -1 ( bit)
C1IMOD :
bits : 2 - 1 ( bit)
C2IMOD :
bits : 4 - 3 ( bit)
C3IMOD : Comparator interrupt mode selection
bits : 6 - 7 (2 bit)
access : read-write
IPOL0 :
bits : 8 - 7 ( bit)
IPOL1 :
bits : 9 - 8 ( bit)
IPOL2 :
bits : 10 - 9 ( bit)
IPOL3 : Comparator outs low/high IRQ selection
bits : 11 - 11 (1 bit)
access : read-write
PPOL0 :
bits : 12 - 11 ( bit)
PPOL1 :
bits : 13 - 12 ( bit)
PPOL2 :
bits : 14 - 13 ( bit)
PPOL3 : Comparator outs for PWM invert selection
bits : 15 - 15 (1 bit)
access : read-write
Comparator Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0IE :
bits : 0 - -1 ( bit)
CMP1IE :
bits : 1 - 0 ( bit)
CMP2IE :
bits : 2 - 1 ( bit)
CMP3IE : Comparator Interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
Comparator Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0IRQ :
bits : 0 - -1 ( bit)
C1IRQ :
bits : 1 - 0 ( bit)
C2IRQ :
bits : 2 - 1 ( bit)
C3IRQ : Comparator interrupt flag
bits : 3 - 3 (1 bit)
access : read-write
C0OUT :
bits : 8 - 7 ( bit)
C1OUT :
bits : 9 - 8 ( bit)
C2OUT :
bits : 10 - 9 ( bit)
C3OUT : Comparator raw output after debounce
bits : 11 - 11 (1 bit)
access : read-only
C0RAW :
bits : 12 - 11 ( bit)
C1RAW :
bits : 13 - 12 ( bit)
C2RAW :
bits : 14 - 13 ( bit)
C3RAW : Comparator raw output before debounce
bits : 15 - 15 (1 bit)
access : read-only
OPAMP 1 Control Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)
OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)
OPAMP 2 Control Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)
OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)
OPAMP 3 Control Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)
OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)
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