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AFE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OPA0CR

CMP0CR

CMP1CR

CMP2CR

CMP3CR

CMPDBR

CMPICR

CMPIER

CMPSR

OPA1CR

OPA2CR

OPA3CR


OPA0CR

OPAMP 0 Control Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA0CR OPA0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN OPAEN

GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)

OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)


CMP0CR

Comparator 0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP0CR CMP0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL CINSEL CMPEN

REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)

CINSEL : Comparator input select
bits : 1 - 1 (1 bit)

CMPEN : Comparator enable(0)/disable(1)
bits : 4 - 4 (1 bit)


CMP1CR

Comparator 1 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP1CR CMP1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL CINSEL CMPEN

REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)

CINSEL : Comparator input select
bits : 1 - 1 (1 bit)

CMPEN : Comparator enable
bits : 4 - 4 (1 bit)


CMP2CR

Comparator 2 Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP2CR CMP2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL CINSEL CMPEN

REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)

CINSEL : Comparator input select
bits : 1 - 1 (1 bit)

CMPEN : Comparator enable
bits : 4 - 4 (1 bit)


CMP3CR

Comparator 3 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP3CR CMP3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL CINSEL CMPEN

REFSEL : Comparator reference selection
bits : 0 - 0 (1 bit)

CINSEL : Comparator input select
bits : 1 - 1 (1 bit)

CMPEN : Comparator enable
bits : 4 - 4 (1 bit)


CMPDBR

Comparator de-bounce Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPDBR CMPDBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0DBNC C1DBNC C2DBNC C3DBNC DBNCTB

C0DBNC :
bits : 0 - -1 ( bit)

C1DBNC :
bits : 4 - 3 ( bit)

C2DBNC :
bits : 8 - 7 ( bit)

C3DBNC : Debouce shift selection
bits : 12 - 15 (4 bit)

DBNCTB : Debounce time base counter
bits : 16 - 23 (8 bit)


CMPICR

Comparator Interrupt Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPICR CMPICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0IMOD C1IMOD C2IMOD C3IMOD IPOL0 IPOL1 IPOL2 IPOL3 PPOL0 PPOL1 PPOL2 PPOL3

C0IMOD :
bits : 0 - -1 ( bit)

C1IMOD :
bits : 2 - 1 ( bit)

C2IMOD :
bits : 4 - 3 ( bit)

C3IMOD : Comparator interrupt mode selection
bits : 6 - 7 (2 bit)
access : read-write

IPOL0 :
bits : 8 - 7 ( bit)

IPOL1 :
bits : 9 - 8 ( bit)

IPOL2 :
bits : 10 - 9 ( bit)

IPOL3 : Comparator outs low/high IRQ selection
bits : 11 - 11 (1 bit)
access : read-write

PPOL0 :
bits : 12 - 11 ( bit)

PPOL1 :
bits : 13 - 12 ( bit)

PPOL2 :
bits : 14 - 13 ( bit)

PPOL3 : Comparator outs for PWM invert selection
bits : 15 - 15 (1 bit)
access : read-write


CMPIER

Comparator Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPIER CMPIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP0IE CMP1IE CMP2IE CMP3IE

CMP0IE :
bits : 0 - -1 ( bit)

CMP1IE :
bits : 1 - 0 ( bit)

CMP2IE :
bits : 2 - 1 ( bit)

CMP3IE : Comparator Interrupt enable
bits : 3 - 3 (1 bit)
access : read-write


CMPSR

Comparator Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPSR CMPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0IRQ C1IRQ C2IRQ C3IRQ C0OUT C1OUT C2OUT C3OUT C0RAW C1RAW C2RAW C3RAW

C0IRQ :
bits : 0 - -1 ( bit)

C1IRQ :
bits : 1 - 0 ( bit)

C2IRQ :
bits : 2 - 1 ( bit)

C3IRQ : Comparator interrupt flag
bits : 3 - 3 (1 bit)
access : read-write

C0OUT :
bits : 8 - 7 ( bit)

C1OUT :
bits : 9 - 8 ( bit)

C2OUT :
bits : 10 - 9 ( bit)

C3OUT : Comparator raw output after debounce
bits : 11 - 11 (1 bit)
access : read-only

C0RAW :
bits : 12 - 11 ( bit)

C1RAW :
bits : 13 - 12 ( bit)

C2RAW :
bits : 14 - 13 ( bit)

C3RAW : Comparator raw output before debounce
bits : 15 - 15 (1 bit)
access : read-only


OPA1CR

OPAMP 1 Control Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA1CR OPA1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN OPAEN

GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)

OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)


OPA2CR

OPAMP 2 Control Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA2CR OPA2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN OPAEN

GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)

OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)


OPA3CR

OPAMP 3 Control Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA3CR OPA3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN OPAEN

GAIN : OPAMP Gain select
bits : 0 - 3 (4 bit)

OPAEN : OPAMP enable
bits : 4 - 4 (1 bit)



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