SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CIDR

WUER

WUSR

RSER

RSSR

PRER1

PRER2

PER1

PER2

PCER1

PCER2

SMR

CSCR

SCCR

CMR

NMIR

COR

PLLCON

VDCCON

LVDCON

IOSCTRIM

SRCR

EOSCR

EMODR

MCCR1

MCCR2

MCCR3

DBCLK1

DBCLK2

DBCLK3

MCCR4

CIDR2


CIDR

Chip ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WUER

Wakeup Source Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDWUE WDTWUE FRTWUE GPIOAWUE GPIOBWUE GPIOCWUE GPIODWUE GPIOEWUE GPIOFWUE

LVDWUE : LVDWUE
bits : 0 - 0

WDTWUE : WDTWUE
bits : 1 - 1

FRTWUE : FRTWUE
bits : 2 - 2

GPIOAWUE : GPIOAWUE
bits : 8 - 8

GPIOBWUE : GPIOBWUE
bits : 9 - 9

GPIOCWUE : GPIOCWUE
bits : 10 - 10

GPIODWUE : GPIODWUE
bits : 11 - 11

GPIOEWUE : GPIOEWUE
bits : 12 - 12

GPIOFWUE : GPIOFWUE
bits : 13 - 13


WUSR

Wakeup Source Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDDWU WDTWU FRTWU GPIOAWU GPIOBWU GPIOCWU GPIODWU GPIOEWU GPIOFWU

LVDDWU : LVDWU
bits : 0 - 0

WDTWU : WDTWU
bits : 1 - 1

FRTWU : FRTWU
bits : 2 - 2

GPIOAWU : GPIOAWU
bits : 8 - 8

GPIOBWU : GPIOBWU
bits : 9 - 9

GPIOCWU : GPIOCWU
bits : 10 - 10

GPIODWU : GPIODWU
bits : 11 - 11

GPIOEWU : GPIOEWU
bits : 12 - 12

GPIOFWU : GPIOFWU
bits : 13 - 13


RSER

Reset Source Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRST XFRST MCKFRST WDTRST SWRST CPURST PINRST

LVDRST : LVD reset enable
bits : 0 - 0

XFRST : external OSC clock failed enable
bits : 1 - 1

MCKFRST : MCLK failed reset enable
bits : 2 - 2

WDTRST : watch dog reset enable
bits : 3 - 3

SWRST : software reset enable
bits : 4 - 4

CPURST : CPU request reset enable
bits : 5 - 5

PINRST : external pin reset enable
bits : 6 - 6


RSSR

Reset Source Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDRST XFRST MCKFRST WDTRST SWRST CPURST PINRST PORST

LVDRST : lvd reset status
bits : 0 - 0

XFRST : clock failed reset status
bits : 1 - 1

MCKFRST : MCLK failed reset status
bits : 2 - 2

WDTRST : watchdog timer reset status
bits : 3 - 3

SWRST : software reset status
bits : 4 - 4

CPURST : cpu request reset status
bits : 5 - 5

PINRST : extenral pin reset status
bits : 6 - 6

PORST : power on reset status
bits : 7 - 7


PRER1

Peripheral Reset Enable Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCU FMC WDT PCU DMA FRT GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TIMER9

SCU : Power Management Unit Reset
bits : 0 - 0

FMC : Flash Memory controll Reset
bits : 1 - 1

WDT : Watch Dog Timer Reset
bits : 2 - 2

PCU : Port controll Reset
bits : 3 - 3

DMA : DMA Reset
bits : 4 - 4

FRT : FRT Reset
bits : 7 - 7

GPIOA : GPIOA Reset
bits : 8 - 8

GPIOB : GPIOB Reset
bits : 9 - 9

GPIOC : GPIOC Reset
bits : 10 - 10

GPIOD : GPIOD Reset
bits : 11 - 11

GPIOE : GPIOE Reset
bits : 12 - 12

GPIOF : GPIOF Reset
bits : 13 - 13

TIMER0 : TIMER0 Reset
bits : 16 - 16

TIMER1 : TIMER1 Reset
bits : 17 - 17

TIMER2 : TIMER2 Reset
bits : 18 - 18

TIMER3 : TIMER3 Reset
bits : 19 - 19

TIMER4 : TIMER4 Reset
bits : 20 - 20

TIMER5 : TIMER5 Reset
bits : 21 - 21

TIMER6 : TIMER6 Reset
bits : 22 - 22

TIMER7 : TIMER7 Reset
bits : 23 - 23

TIMER8 : TIMER8 Reset
bits : 24 - 24

TIMER9 : TIMER9 Reset
bits : 25 - 25


PRER2

Peripheral Reset Enable Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 SPI1 IIC0 IIC1 UART0 UART1 UART2 UART3 MPWM0 MPWM1 ADC0 ADC1

SPI0 : SPI0 Reset
bits : 0 - 0

SPI1 : SPI1 Reset
bits : 1 - 1

IIC0 : IIC0 Reset
bits : 4 - 4

IIC1 : IIC1 Reset
bits : 5 - 5

UART0 : UART0 Reset
bits : 8 - 8

UART1 : UART1
bits : 9 - 9

UART2 : UART2
bits : 10 - 10

UART3 : UART3
bits : 11 - 11

MPWM0 : MPWM0 Reset
bits : 16 - 16

MPWM1 : MPWM1 Reset
bits : 17 - 17

ADC0 : ADC0 Reset
bits : 20 - 20

ADC1 : ADC1 Reset
bits : 21 - 21


PER1

Peripheral Enable Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA FRT GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TIMER9

DMA : DMA Function Enable
bits : 4 - 4

FRT : FRT
bits : 7 - 7

GPIOA : GPIOA
bits : 8 - 8

GPIOB : GPIOB
bits : 9 - 9

GPIOC : GPIOC
bits : 10 - 10

GPIOD : GPIOD
bits : 11 - 11

GPIOE : GPIOE
bits : 12 - 12

GPIOF : GPIOF
bits : 13 - 13

TIMER0 : TIMER0
bits : 16 - 16

TIMER1 : TIMER1
bits : 17 - 17

TIMER2 : TIMER2
bits : 18 - 18

TIMER3 : TIMER3
bits : 19 - 19

TIMER4 : TIMER4 Enable
bits : 20 - 20

TIMER5 : TIMER5 Enable
bits : 21 - 21

TIMER6 : TIMER6 Enable
bits : 22 - 22

TIMER7 : TIMER7 Enable
bits : 23 - 23

TIMER8 : TIMER8 Enable
bits : 24 - 24

TIMER9 : TIMER9 Enable
bits : 25 - 25


PER2

Peripheral Enable Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 SPI1 I2C0 I2C1 UART0 UART1 UART2 UART3 MPWM0 MPWM1 ADC0 ADC1

SPI0 : SPI0 Enable
bits : 0 - 0

SPI1 : SPI1 Enable
bits : 1 - 1

I2C0 : I2C0 Enable
bits : 4 - 4

I2C1 : I2C1 Enable
bits : 5 - 5

UART0 : UART0 Enable
bits : 8 - 8

UART1 : UART1 Enable
bits : 9 - 9

UART2 : UART2 Enable
bits : 10 - 10

UART3 : UART3 Enable
bits : 11 - 11

MPWM0 : MPWM0 Enable
bits : 16 - 16

MPWM1 : MPWM1 Enable
bits : 17 - 17

ADC0 : ADC0
bits : 20 - 20

ADC1 : ADC1
bits : 21 - 21


PCER1

Peripheral Clock Enable Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA FRT GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TIMER9

DMA : DMA Function Enable
bits : 4 - 4

FRT : FRT Enable
bits : 7 - 7

GPIOA : GPIOA
bits : 8 - 8

GPIOB : GPIOB
bits : 9 - 9

GPIOC : GPIOC
bits : 10 - 10

GPIOD : GPIOD
bits : 11 - 11

GPIOE : GPIOE
bits : 12 - 12

GPIOF : GPIOF
bits : 13 - 13

TIMER0 : TIMER0
bits : 16 - 16

TIMER1 : TIMER1
bits : 17 - 17

TIMER2 : TIMER2
bits : 18 - 18

TIMER3 : TIMER3
bits : 19 - 19

TIMER4 : TIMER5 Enable
bits : 20 - 20

TIMER5 : TIMER5 Enable
bits : 21 - 21

TIMER6 : TIMER6 Enable
bits : 22 - 22

TIMER7 : TIMER7 Enable
bits : 23 - 23

TIMER8 : TIMER8 Enable
bits : 24 - 24

TIMER9 : TIMER9 Enable
bits : 25 - 25


PCER2

Peripheral Clock Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 SPI1 I2C0 I2C1 UART0 UART1 UART2 UART3 MPWM0 MPWM1 ADC0 ADC1

SPI0 : SPI0 Enable
bits : 0 - 0

SPI1 : SPI1 Enable
bits : 1 - 1

I2C0 : I2C0 Enable
bits : 4 - 4

I2C1 : I2C1 Enable
bits : 5 - 5

UART0 : UART0 Enable
bits : 8 - 8

UART1 : UART1 Enable
bits : 9 - 9

UART2 : UART2 Enable
bits : 10 - 10

UART3 : UART3 Enable
bits : 11 - 11

MPWM0 : MPWM0 Enable
bits : 16 - 16

MPWM1 : MPWM1 Enable
bits : 17 - 17

ADC0 : ADC0
bits : 20 - 20

ADC1 : ADC1
bits : 21 - 21


SMR

System Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREVMODE VDCAON

PREVMODE : PREVMODE
bits : 4 - 5

VDCAON : VDCAON
bits : 8 - 8


CSCR

Clock Source Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOSCON IOSCCON RINGOSCCON SXOSCEN

EOSCON : External crystal OSC control
bits : 0 - 1

IOSCCON : Internal OSC control
bits : 2 - 3

RINGOSCCON : Internal ring OSC control
bits : 4 - 5

SXOSCEN : External Sub Oscillator Enable
bits : 7 - 7


SCCR

System Clock Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCLKSEL FINSEL

MCLKSEL : System clock select
bits : 0 - 1

FINSEL : PLL Input source FIN Select
bits : 2 - 2


CMR

Clock Monitoring Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOSCSTS EOSCFAIL EOSCIE EOSCMNT MCLKSTS MCLKFAIL MCLKIE MCLKMNT SX0SCSTS SX0SCFAIL SX0SCIE SX0SCMNT MCLKREC

EOSCSTS : external OSC status
bits : 0 - 0
access : read-write

EOSCFAIL : external OSC failed flag
bits : 1 - 1
access : read-write

EOSCIE : external OSC failed interrupt enable
bits : 2 - 2
access : read-write

EOSCMNT : Externaler OSC monitor enable
bits : 3 - 3
access : read-write

MCLKSTS : MCLK clock status
bits : 4 - 4
access : read-write

MCLKFAIL : MCLK Failed flag
bits : 5 - 5
access : read-write

MCLKIE : MCLK fail Interrupt enable
bits : 6 - 6
access : read-write

MCLKMNT : MCLK monitor enable
bits : 7 - 7
access : read-write

SX0SCSTS : Sub Oscillator clock status
bits : 8 - 8
access : read-write

SX0SCFAIL : Sub Oscillator Fail Interrupt
bits : 9 - 9
access : read-write

SX0SCIE : Sub Oscillator Fail Interrupt Enable
bits : 10 - 10
access : read-write

SX0SCMNT : Sub Oscillator Monitoring Enable
bits : 11 - 11
access : read-write

MCLKREC : MCLK failed auto recovery
bits : 15 - 15
access : read-only


NMIR

NMI Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODEN MCLKFAILEN WDTINTEN OVP0EN PROT0EN OVP1EN PROT1EN NMIPINEN BODSTS MCLKFAILSTS WDTINTSTS OVP0STS PROT0STS OVP1STS PROT1STS NMIINTSTS NMIPINDBEN NMIINT NMIPINSTS

BODEN : Brown Out Dectect NMI Enable
bits : 0 - 0
access : read-write

MCLKFAILEN : MCLK Fail NMI Enable
bits : 1 - 1
access : read-write

WDTINTEN : WDT interrupt for NMI Enable
bits : 2 - 2
access : read-write

OVP0EN : Over Voltage Protection NMI Enable
bits : 3 - 3
access : read-write

PROT0EN : Protection Condition NMI Enable
bits : 4 - 4
access : read-write

OVP1EN : Over Voltage Protection NMI Enable
bits : 5 - 5
access : read-write

PROT1EN : Protection Condition NMI Enable
bits : 6 - 6
access : read-write

NMIPINEN : NMI Pin Enable
bits : 7 - 7
access : read-write

BODSTS : Brown Out Detect Status
bits : 8 - 8
access : read-only

MCLKFAILSTS : MCLK Fail Status
bits : 9 - 9
access : read-only

WDTINTSTS : Watch Dog status
bits : 10 - 10
access : read-only

OVP0STS : Over Voltage Protection Status
bits : 11 - 11
access : read-only

PROT0STS : Protection condition status
bits : 12 - 12
access : read-only

OVP1STS : Over Voltage Protection Status
bits : 13 - 13
access : read-only

PROT1STS : Protection condition status
bits : 14 - 14
access : read-only

NMIINTSTS : NMI Interrupt Status
bits : 15 - 15
access : read-only

NMIPINDBEN : NMI Pin Debounce status
bits : 17 - 17
access : read-write

NMIINT : NMI Interrupt state
bits : 18 - 18
access : read-write

NMIPINSTS : NMI Pin status
bits : 19 - 19
access : read-only


COR

Clock Output Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKODIV CLKOEN

CLKODIV : clock output divider value
bits : 0 - 3
access : read-write

CLKOEN : clock output enable
bits : 4 - 4
access : read-write


PLLCON

PLL Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSTDIV FBCTRL PREDIV LOCK BYPASS PLLEN PLLRSTB

POSTDIV : post divider
bits : 0 - 3
access : read-write

FBCTRL : Feedback control
bits : 4 - 7
access : read-write

PREDIV : FIN pre divider
bits : 8 - 8
access : read-write

LOCK : PLL Lock state
bits : 12 - 12
access : read-only

BYPASS : FIN Bypass to FOUT
bits : 13 - 13
access : read-write

PLLEN : PLL Enable
bits : 14 - 14
access : read-write

PLLRSTB : PLL reset
bits : 15 - 15
access : read-write


VDCCON

VDC Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDCWDLY VDCDE VDCTRIM VDCTE BMRTRIM BMRTE

VDCWDLY : VDC warm up delay count
bits : 0 - 7
access : read-write

VDCDE : VDCDE
bits : 8 - 8
access : write-only

VDCTRIM : VDCTRIM
bits : 16 - 19
access : read-write

VDCTE : VDC Trim Write Enable
bits : 23 - 23
access : write-only

BMRTRIM : BMRTRIM
bits : 24 - 26
access : read-write

BMRTE : BMRTE
bits : 31 - 31
access : write-only


LVDCON

Brown out detect Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODEN BODLVL BODSEL SELEN BODTRIM BODTE

BODEN : Brown out detection Enable
bits : 0 - 0
access : read-write

BODLVL : BODLVL
bits : 1 - 1
access : read-only

BODSEL : Brown Out Level Select
bits : 8 - 9
access : read-write

SELEN : SELEN
bits : 15 - 15
access : read-write

BODTRIM : BODTRIM
bits : 16 - 17
access : read-write

BODTE : BODTE
bits : 23 - 23
access : write-only


IOSCTRIM

Internal OSC Trim Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDCL UDCH UDCEN LTM LT LTEN TSL TSLEN

UDCL : UDCL
bits : 0 - 2

UDCH : UDCH
bits : 3 - 4

UDCEN : UDCEN
bits : 7 - 7

LTM : interal oscillator LT trim value
bits : 8 - 9

LT : interal oscillator LT trim value
bits : 10 - 13

LTEN : LTEN
bits : 15 - 15

TSL : TSL
bits : 16 - 18

TSLEN : TSLEN
bits : 23 - 23


SRCR

System Reset Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST STBYOP

SWRST : Internal soft reset activation
bits : 0 - 0
access : write-only

STBYOP : STBOP pin output polarity select bit
bits : 4 - 4


EOSCR

External Oscillator Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCSEL NCEN ISEL ISELEN

NCSEL : Select Noise Canceling delay
bits : 0 - 1
access : read-write

NCEN : write enable for Noise Canceling delay
bits : 7 - 7
access : write-only

ISEL : select current
bits : 8 - 9
access : read-write

ISELEN : write enable for bit field ISEL
bits : 15 - 15
access : write-only


EMODR

External Mode Status Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOT TEST SCANMD

BOOT : boot pin level
bits : 0 - 0

TEST : TEST PIN level
bits : 1 - 1

SCANMD : scan mode pin level
bits : 2 - 2


MCCR1

Trace and SysTick Clock Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STDIV STCSEL TRACEDIV TRCSEL TRCPOL

STDIV : systick divider
bits : 0 - 7
access : read-write

STCSEL : systick clock source sel
bits : 8 - 10
access : read-write

TRACEDIV : TRACEDIV
bits : 16 - 23
access : read-write

TRCSEL : trace clock source sel
bits : 24 - 26
access : read-write

TRCPOL : TRCPOL
bits : 31 - 31
access : write-only


MCCR2

MPWM0 and MPWM1 Clock Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0DIV PWM0CSEL PWM1DIV PWM1CSEL

PWM0DIV : PWM0 divider
bits : 0 - 7

PWM0CSEL : pwm0 clock sel
bits : 8 - 10

PWM1DIV : pwm1 divider
bits : 16 - 23

PWM1CSEL : PWM1 clock sel
bits : 24 - 26


MCCR3

TEXT0 and WDT clock control registers
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTDIV WDTCSEL TEXT0DIV TEXT0CSEL

WDTDIV : WDT divider
bits : 0 - 7

WDTCSEL : WDT clock sel
bits : 8 - 10

TEXT0DIV : timer ext0 divider
bits : 16 - 23

TEXT0CSEL : timer ext0 clock sel
bits : 24 - 26


DBCLK1

PA and PB Debounce Clock Control Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDIV PADCSEL PBDDIV PBDSEL

PADDIV : PORT A debounce divider
bits : 0 - 7

PADCSEL : debouce clock for port A source clock sel
bits : 8 - 10

PBDDIV : PORT B debounce divider
bits : 16 - 23

PBDSEL : debouce clock for port B source clock sel
bits : 24 - 26


DBCLK2

PC and PD Debounce Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCDDIV PCDCSEL PDDDIV PDDCSEL

PCDDIV : PORT C debounce divider
bits : 0 - 7

PCDCSEL : debouce clock for port C source clock sel
bits : 8 - 10

PDDDIV : PORT D debounce divider
bits : 16 - 23

PDDCSEL : debouce clock for port D source clock sel
bits : 24 - 26


DBCLK3

PE and PF Debounce Clock Control
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEDDIV PEDCSEL PFDDIV PFDCSEL

PEDDIV : PORT E Debounce clock divider
bits : 0 - 7

PEDCSEL : Debouce clock for PORT E source select bit
bits : 8 - 10

PFDDIV : PORT F Clock N divider
bits : 16 - 23

PFDCSEL : Debounce Clock for PORT F source select bitl
bits : 24 - 26


MCCR4

Alternative ADC and NMI Debounce Clock control
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIDDIV NMICSEL ADCCDIV ADCCSEL

NMIDDIV : NMI Debounce clock divider
bits : 0 - 7

NMICSEL : Debouce clock for NMI source select bit
bits : 8 - 10

ADCCDIV : ADC Clock N divider
bits : 16 - 23

ADCCSEL : ADC clock source select
bits : 24 - 26


CIDR2

Revision ID Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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