\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Timer Load Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Watchdog Timer Current Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Watchdog Timer Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPRS : counter prescaler
bits : 0 - 2 (3 bit)
CKSEL : WDTCLKIN clock source select
bits : 3 - 3 (1 bit)
WDTEN : WDT counter enable
bits : 4 - 4 (1 bit)
WDTRE : WDT interrupt reset
bits : 6 - 6 (1 bit)
WDTIE : WDT interrupt enable
bits : 7 - 7 (1 bit)
WUF : WDT underflow falg
bits : 8 - 8 (1 bit)
WDBG : WDT operation in debug mode
bits : 15 - 15 (1 bit)
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