\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Free Run Timer Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIE : MatchInterrupt Enable
bits : 0 - 0 (1 bit)
OVIE : Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
MCD : Counter Match clear Disable flag
bits : 2 - 2 (1 bit)
CLKSEL : FRT Counter clock source
bits : 3 - 4 (2 bit)
Free Run Timer Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIF : Match Interrupt flag
bits : 0 - 0 (1 bit)
OVIF : Overflow Interrupt flag
bits : 1 - 1 (1 bit)
RACK : Read Counter Acknowledge bit
bits : 2 - 2 (1 bit)
Free Run Timer Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEN : FRT Enable
bits : 0 - 0 (1 bit)
FHOLD : Counter Register Hold
bits : 1 - 1 (1 bit)
FCLR : Counter Register Clear
bits : 2 - 2 (1 bit)
CNTREQ : FRT Counter Read Request bitr
bits : 3 - 3 (1 bit)
Free Run Timer Period Match Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : FRT Match Data
bits : 0 - 31 (32 bit)
Free Run Timer Counter Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.