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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DR

CR

SCLL

SCLH

SDH

SR

SAR


DR

I2C Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : Data
bits : 0 - 7 (8 bit)


CR

I2C Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP ACKEN INTEN SOFTRST I2CEN IIF INTDEL

START : transmission start bit in master mode
bits : 0 - 0 (1 bit)

STOP : Stop enable bit
bits : 1 - 1 (1 bit)

ACKEN : ACK enabit bit in receiver mode
bits : 3 - 3 (1 bit)

INTEN : Interrupt enable bit
bits : 4 - 4 (1 bit)

SOFTRST : Soft reset enable bit
bits : 5 - 5 (1 bit)

I2CEN : I2C Enable Bit
bits : 6 - 6 (1 bit)

IIF : Interrupt Flag
bits : 7 - 7 (1 bit)

INTDEL : Interval delay between Addr and Data
bits : 8 - 9 (2 bit)


SCLL

I2C SCL LOW duration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLL SCLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLL

SCLL : SCL Low duration value
bits : 0 - 15 (16 bit)


SCLH

I2C SCL HIGH duration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLH SCLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLH

SCLH : SCL High duration value
bits : 0 - 15 (16 bit)


SDH

SDA Hold Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDH SDH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDH

SDH : SDA Hold time
bits : 0 - 14 (15 bit)


SR

Status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXACK TMODE BUSY MLOST SSEL STOP TEND GCALL

RXACK : RX ack flag
bits : 0 - 0 (1 bit)

TMODE : Transmit/reciever mode flag
bits : 1 - 1 (1 bit)

BUSY : busy flag
bits : 2 - 2 (1 bit)

MLOST : Mastership lost flag
bits : 3 - 3 (1 bit)

SSEL : slave flag (start condition received)
bits : 4 - 4 (1 bit)

STOP : Stop Flag
bits : 5 - 5 (1 bit)

TEND : 1 byte transmission complete flag
bits : 6 - 6 (1 bit)

GCALL : General call flag
bits : 7 - 7 (1 bit)


SAR

I2C Slave Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR SAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCEN SVAD

GCEN : general call enable bit
bits : 0 - 0 (1 bit)

SVAD : 7 bits slave address
bits : 1 - 7 (7 bit)



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