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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

SCSR

CR

SR

IER

DDR

DR0

DR1

DR2

DR3

CSCR

DR4

DR5

DR6

DR7

CR1

TRG


MR

ADCn Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL ADCMOD ARST ADEN SEQCNT STSEL DMAEN DMACH

TRGSEL : ADC Trigger source sel
bits : 0 - 1 (2 bit)

ADCMOD : ADC convert mode
bits : 4 - 5 (2 bit)

ARST : Stop at end of sequence
bits : 6 - 6 (1 bit)

ADEN : ADC Enable
bits : 7 - 7 (1 bit)

SEQCNT : Sequence count
bits : 8 - 10 (3 bit)

STSEL : Sampling Time Selection
bits : 12 - 16 (5 bit)

DMAEN : DMA Enable
bits : 17 - 17 (1 bit)

DMACH : DMA Channel option
bits : 18 - 18 (1 bit)


SCSR

ADC Sequence Channel select
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQ0CH SEQ1CH SEQ2CH SEQ3CH SEQ4CH SEQ5CH SEQ6CH SEQ7CH

SEQ0CH : 1st sequence coversion channel selection
bits : 0 - 3 (4 bit)

SEQ1CH : 2nd sequence coversion channel selection
bits : 4 - 7 (4 bit)

SEQ2CH : 3rd sequence coversion channel selection
bits : 8 - 11 (4 bit)

SEQ3CH : 4th sequence coversion channel selection
bits : 12 - 15 (4 bit)

SEQ4CH : 5th sequence coversion channel selection
bits : 16 - 19 (4 bit)

SEQ5CH : 6th sequence coversion channel selection
bits : 20 - 23 (4 bit)

SEQ6CH : 7th sequence coversion channel selection
bits : 24 - 27 (4 bit)

SEQ7CH : 8th sequence coversion channel selection
bits : 28 - 31 (4 bit)


CR

ADCn Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START ASTOP

START : ADC conversion start
bits : 0 - 0 (1 bit)
access : read-write

ASTOP : ADC Stop
bits : 7 - 7 (1 bit)
access : write-only


SR

ADC Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOCIRQ EOSIRQ TRGIRQ DMAIRQ DOVRUN ABUSY EOC

EOCIRQ : Each conversion in sequence interrupt flag
bits : 0 - 0 (1 bit)

EOSIRQ : End of Sequence interrupt flag
bits : 2 - 2 (1 bit)

TRGIRQ : ADC Trigger interrupt flag
bits : 3 - 3 (1 bit)

DMAIRQ : DMA received/transfer is done
bits : 4 - 4 (1 bit)

DOVRUN : DMA overrun flag
bits : 5 - 5 (1 bit)
access : read-only

ABUSY : ADC conversion busy flag
bits : 6 - 6 (1 bit)
access : read-only

EOC : End of Conversion Flag
bits : 7 - 7 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOCIRQE EOSIRQE TRGIRQE DMAIRQE

EOCIRQE : Conversion Complete interrupt enable
bits : 0 - 0 (1 bit)

EOSIRQE : ADC End of Sequence interrupt enable
bits : 2 - 2 (1 bit)

TRGIRQE : ADC Trigger conversion intterupt enable
bits : 3 - 3 (1 bit)

DMAIRQE : DMA done interrupt enable
bits : 4 - 4 (1 bit)


DDR

ADC DMA Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DDR DDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADMACH ADDMAR

ADMACH : ADC data channel indicator
bits : 0 - 3 (4 bit)

ADDMAR : ADC conversion result data
bits : 4 - 15 (12 bit)


DR0

ADC Sequence Data Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR0 DR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


DR1

ADC Sequence Data Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR1 DR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


DR2

ADC Sequence Data Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR2 DR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


DR3

ADC Sequence Data Register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR3 DR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


CSCR

ADCn Current Sequence/Channel Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCR CSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACH CSEQN

CACH : Current Active Channel
bits : 0 - 3 (4 bit)
access : read-only

CSEQN : Current Sequence Number
bits : 4 - 6 (3 bit)


DR4

ADC Sequence Data Register 5
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR4 DR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


DR5

ADC Sequence Data Register 6
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR5 DR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


DR6

ADC Sequence Data Register 7
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR6 DR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


DR7

ADC Sequence Data Register 8
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR7 DR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCDATA

ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)


CR1

ADCn Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKINVT EXTCLK ADCPD CLKDIV ADCPDA

CLKINVT : divided clock inversion
bits : 5 - 5 (1 bit)

EXTCLK : ADCuse external clock
bits : 6 - 6 (1 bit)

ADCPD : ADC Power down
bits : 7 - 7 (1 bit)

CLKDIV : ADC clock divider
bits : 8 - 14 (7 bit)

ADCPDA : ADC R-ADC disable to save power
bits : 15 - 15 (1 bit)


TRG

ADC Trigger Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRG TRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQTRG0 SEQTRG1 SEQTRG2 SEQTRG3 SEQTRG4 SEQTRG5 SEQTRG6 SEQTRG7

SEQTRG0 : Sequence Trigger 0
bits : 0 - 2 (3 bit)

SEQTRG1 : Sequence Trigger 1
bits : 4 - 6 (3 bit)

SEQTRG2 : Sequence Trigger 2
bits : 8 - 10 (3 bit)

SEQTRG3 : Sequence Trigger 3
bits : 12 - 14 (3 bit)

SEQTRG4 : Sequence Trigger 4
bits : 16 - 18 (3 bit)

SEQTRG5 : Sequence Trigger 5
bits : 20 - 22 (3 bit)

SEQTRG6 : Sequence Trigger 6
bits : 24 - 26 (3 bit)

SEQTRG7 : Sequence Trigger 7
bits : 28 - 30 (3 bit)



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