\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
ADCn Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : ADC Trigger source sel
bits : 0 - 1 (2 bit)
ADCMOD : ADC convert mode
bits : 4 - 5 (2 bit)
ARST : Stop at end of sequence
bits : 6 - 6 (1 bit)
ADEN : ADC Enable
bits : 7 - 7 (1 bit)
SEQCNT : Sequence count
bits : 8 - 10 (3 bit)
STSEL : Sampling Time Selection
bits : 12 - 16 (5 bit)
DMAEN : DMA Enable
bits : 17 - 17 (1 bit)
DMACH : DMA Channel option
bits : 18 - 18 (1 bit)
ADC Sequence Channel select
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQ0CH : 1st sequence coversion channel selection
bits : 0 - 3 (4 bit)
SEQ1CH : 2nd sequence coversion channel selection
bits : 4 - 7 (4 bit)
SEQ2CH : 3rd sequence coversion channel selection
bits : 8 - 11 (4 bit)
SEQ3CH : 4th sequence coversion channel selection
bits : 12 - 15 (4 bit)
SEQ4CH : 5th sequence coversion channel selection
bits : 16 - 19 (4 bit)
SEQ5CH : 6th sequence coversion channel selection
bits : 20 - 23 (4 bit)
SEQ6CH : 7th sequence coversion channel selection
bits : 24 - 27 (4 bit)
SEQ7CH : 8th sequence coversion channel selection
bits : 28 - 31 (4 bit)
ADCn Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : ADC conversion start
bits : 0 - 0 (1 bit)
access : read-write
ASTOP : ADC Stop
bits : 7 - 7 (1 bit)
access : write-only
ADC Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCIRQ : Each conversion in sequence interrupt flag
bits : 0 - 0 (1 bit)
EOSIRQ : End of Sequence interrupt flag
bits : 2 - 2 (1 bit)
TRGIRQ : ADC Trigger interrupt flag
bits : 3 - 3 (1 bit)
DMAIRQ : DMA received/transfer is done
bits : 4 - 4 (1 bit)
DOVRUN : DMA overrun flag
bits : 5 - 5 (1 bit)
access : read-only
ABUSY : ADC conversion busy flag
bits : 6 - 6 (1 bit)
access : read-only
EOC : End of Conversion Flag
bits : 7 - 7 (1 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCIRQE : Conversion Complete interrupt enable
bits : 0 - 0 (1 bit)
EOSIRQE : ADC End of Sequence interrupt enable
bits : 2 - 2 (1 bit)
TRGIRQE : ADC Trigger conversion intterupt enable
bits : 3 - 3 (1 bit)
DMAIRQE : DMA done interrupt enable
bits : 4 - 4 (1 bit)
ADC DMA Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADMACH : ADC data channel indicator
bits : 0 - 3 (4 bit)
ADDMAR : ADC conversion result data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADCn Current Sequence/Channel Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACH : Current Active Channel
bits : 0 - 3 (4 bit)
access : read-only
CSEQN : Current Sequence Number
bits : 4 - 6 (3 bit)
ADC Sequence Data Register 5
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 6
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 7
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADC Sequence Data Register 8
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCDATA : ADC Sequence Data
bits : 4 - 15 (12 bit)
ADCn Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKINVT : divided clock inversion
bits : 5 - 5 (1 bit)
EXTCLK : ADCuse external clock
bits : 6 - 6 (1 bit)
ADCPD : ADC Power down
bits : 7 - 7 (1 bit)
CLKDIV : ADC clock divider
bits : 8 - 14 (7 bit)
ADCPDA : ADC R-ADC disable to save power
bits : 15 - 15 (1 bit)
ADC Trigger Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQTRG0 : Sequence Trigger 0
bits : 0 - 2 (3 bit)
SEQTRG1 : Sequence Trigger 1
bits : 4 - 6 (3 bit)
SEQTRG2 : Sequence Trigger 2
bits : 8 - 10 (3 bit)
SEQTRG3 : Sequence Trigger 3
bits : 12 - 14 (3 bit)
SEQTRG4 : Sequence Trigger 4
bits : 16 - 18 (3 bit)
SEQTRG5 : Sequence Trigger 5
bits : 20 - 22 (3 bit)
SEQTRG6 : Sequence Trigger 6
bits : 24 - 26 (3 bit)
SEQTRG7 : Sequence Trigger 7
bits : 28 - 30 (3 bit)
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