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RCM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ICC

MCC

CSC

CLKDIV

APBEN1

CSS

COC

APBEN2

HIRCTRIM

RSTSTS

APBEN3

ECC

MCS


ICC

Internal Clocks Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICC ICC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HIRCEN HIRCRF FWFHEN LIRCEN LIRCRF RPOEN

HIRCEN : High speed internal RC oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

HIRCRF : High speed internal RC oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

FWFHEN : Fast Wake-up from Active Halt/Halt mode
bits : 2 - 2 (1 bit)
access : read-write

LIRCEN : Low speed internal RC oscillator enable
bits : 3 - 3 (1 bit)
access : read-write

LIRCRF : Low speed internal oscillator ready
bits : 4 - 4 (1 bit)
access : read-only

RPOEN : Slow Wake-up from Active Halt/Halt modes
bits : 5 - 5 (1 bit)
access : read-write


MCC

Clock Master Switch Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCC MCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCC

MCC : Clock master selection bits
bits : 0 - 7 (8 bit)


CSC

Switch Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSC CSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSBF CSEN CSIE CSIF

CSBF : Switch busy flag
bits : 0 - 0 (1 bit)

CSEN : Switch start/stop
bits : 1 - 1 (1 bit)

CSIE : Clock switch interrupt enable
bits : 2 - 2 (1 bit)

CSIF : Clock switch interrupt flag
bits : 3 - 3 (1 bit)


CLKDIV

Clock Divider Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUDIV HIRCDIV HDS

CPUDIV : High speed internal clock prescaler
bits : 0 - 2 (3 bit)

HIRCDIV : CPU clock prescaler
bits : 3 - 4 (2 bit)

HDS : HDS
bits : 5 - 5 (1 bit)


APBEN1

APB peripheral clock enable register1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBEN1 APBEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2CCEN SPICEN UART1CEN TMR4CEN TMR2CEN TMR1CEN

I2CCEN : I2C clock enable
bits : 0 - 0 (1 bit)

SPICEN : SPI clock enable
bits : 1 - 1 (1 bit)

UART1CEN : UART1 clock enabl
bits : 3 - 3 (1 bit)

TMR4CEN : Timer 4 clock enable
bits : 4 - 4 (1 bit)

TMR2CEN : Timer 2 clock enable
bits : 5 - 5 (1 bit)

TMR1CEN : Timer 1 clock enable
bits : 7 - 7 (1 bit)


CSS

Clock security system register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSS CSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSSEN BCEN CSSFDIE CSSFDIF

CSSEN : Clock security system enable
bits : 0 - 0 (1 bit)
access : read-write

BCEN : Auxiliary oscillator connected to master clock
bits : 1 - 1 (1 bit)
access : read-only

CSSFDIE : Clock security system detection interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

CSSFDIF : Clock security system detection
bits : 3 - 3 (1 bit)
access : read-write


COC

clock output control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COC COC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COEN COS CORF COBF

COEN : Configurable clock output enable
bits : 0 - 0 (1 bit)
access : read-write

COS : Configurable clock output selection
bits : 1 - 4 (4 bit)
access : read-write

CORF : Configurable clock output ready
bits : 5 - 5 (1 bit)
access : read-only

COBF : Configurable clock output busy
bits : 6 - 6 (1 bit)
access : read-only


APBEN2

APB peripheral clock enable register2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBEN2 APBEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUPTCEN ADCCEN

WUPTCEN : AWU clock enable
bits : 2 - 2 (1 bit)

ADCCEN : ADC clock enable
bits : 3 - 3 (1 bit)


HIRCTRIM

HIRC clock calibration trimming register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIRCTRIM HIRCTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : High speed internal oscillator trimmer
bits : 0 - 3 (4 bit)


RSTSTS

Reset status register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSTS RSTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTRF IWDTRF EMCRF

WWDTRF : WWDG reset flag bit mask
bits : 0 - 0 (1 bit)

IWDTRF : IWDG reset flag bit mask
bits : 1 - 1 (1 bit)

EMCRF : EMC reset flag bit mask
bits : 4 - 4 (1 bit)


APBEN3

APB peripheral clock enable register3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBEN3 APBEN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR1ACEN UART2CEN UART3CEN

TMR1ACEN : TMR1 clock enable
bits : 0 - 0 (1 bit)

UART2CEN : UART2 clock enable
bits : 1 - 1 (1 bit)

UART3CEN : UART3 clock enable
bits : 4 - 4 (1 bit)


ECC

External Interrupt Control Register for PORTE and TLI
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC ECC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HXTEN HXTRF

HXTEN : High speed external crystal oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

HXTRF : High speed external crystal oscillator ready
bits : 1 - 1 (1 bit)
access : read-only


MCS

Clock Master Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MCS MCS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCS

MCS : Clock master status bits
bits : 0 - 7 (8 bit)



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