\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Internal Clocks Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIRCEN : High speed internal RC oscillator enable
bits : 0 - 0 (1 bit)
access : read-write
HIRCRF : High speed internal RC oscillator ready
bits : 1 - 1 (1 bit)
access : read-only
FWFHEN : Fast Wake-up from Active Halt/Halt mode
bits : 2 - 2 (1 bit)
access : read-write
LIRCEN : Low speed internal RC oscillator enable
bits : 3 - 3 (1 bit)
access : read-write
LIRCRF : Low speed internal oscillator ready
bits : 4 - 4 (1 bit)
access : read-only
RPOEN : Slow Wake-up from Active Halt/Halt modes
bits : 5 - 5 (1 bit)
access : read-write
Clock Master Switch Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCC : Clock master selection bits
bits : 0 - 7 (8 bit)
Switch Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSBF : Switch busy flag
bits : 0 - 0 (1 bit)
CSEN : Switch start/stop
bits : 1 - 1 (1 bit)
CSIE : Clock switch interrupt enable
bits : 2 - 2 (1 bit)
CSIF : Clock switch interrupt flag
bits : 3 - 3 (1 bit)
Clock Divider Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUDIV : High speed internal clock prescaler
bits : 0 - 2 (3 bit)
HIRCDIV : CPU clock prescaler
bits : 3 - 4 (2 bit)
HDS : HDS
bits : 5 - 5 (1 bit)
APB peripheral clock enable register1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CCEN : I2C clock enable
bits : 0 - 0 (1 bit)
SPICEN : SPI clock enable
bits : 1 - 1 (1 bit)
UART1CEN : UART1 clock enabl
bits : 3 - 3 (1 bit)
TMR4CEN : Timer 4 clock enable
bits : 4 - 4 (1 bit)
TMR2CEN : Timer 2 clock enable
bits : 5 - 5 (1 bit)
TMR1CEN : Timer 1 clock enable
bits : 7 - 7 (1 bit)
Clock security system register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSEN : Clock security system enable
bits : 0 - 0 (1 bit)
access : read-write
BCEN : Auxiliary oscillator connected to master clock
bits : 1 - 1 (1 bit)
access : read-only
CSSFDIE : Clock security system detection interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
CSSFDIF : Clock security system detection
bits : 3 - 3 (1 bit)
access : read-write
clock output control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEN : Configurable clock output enable
bits : 0 - 0 (1 bit)
access : read-write
COS : Configurable clock output selection
bits : 1 - 4 (4 bit)
access : read-write
CORF : Configurable clock output ready
bits : 5 - 5 (1 bit)
access : read-only
COBF : Configurable clock output busy
bits : 6 - 6 (1 bit)
access : read-only
APB peripheral clock enable register2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUPTCEN : AWU clock enable
bits : 2 - 2 (1 bit)
ADCCEN : ADC clock enable
bits : 3 - 3 (1 bit)
HIRC clock calibration trimming register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : High speed internal oscillator trimmer
bits : 0 - 3 (4 bit)
Reset status register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTRF : WWDG reset flag bit mask
bits : 0 - 0 (1 bit)
IWDTRF : IWDG reset flag bit mask
bits : 1 - 1 (1 bit)
EMCRF : EMC reset flag bit mask
bits : 4 - 4 (1 bit)
APB peripheral clock enable register3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR1ACEN : TMR1 clock enable
bits : 0 - 0 (1 bit)
UART2CEN : UART2 clock enable
bits : 1 - 1 (1 bit)
UART3CEN : UART3 clock enable
bits : 4 - 4 (1 bit)
External Interrupt Control Register for PORTE and TLI
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : High speed external crystal oscillator enable
bits : 0 - 0 (1 bit)
access : read-write
HXTRF : High speed external crystal oscillator ready
bits : 1 - 1 (1 bit)
access : read-only
Clock Master Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCS : Clock master status bits
bits : 0 - 7 (8 bit)
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