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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

STS

CTRL1

CTRL2

CTRL3

CTRL4

CTRL5

GTS

DIV

SW

IOSW2

DATA

BR1

BR0


STS

Status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEF FEF NEF OEF IDLEF RXBNEF TXCF TXBEF

PEF : Parity error
bits : 0 - 0 (1 bit)
access : read-only

FEF : Framing error
bits : 1 - 1 (1 bit)
access : read-only

NEF : Noise error flag
bits : 2 - 2 (1 bit)
access : read-only

OEF : Overrun error
bits : 3 - 3 (1 bit)
access : read-only

IDLEF : IDLE line detected
bits : 4 - 4 (1 bit)
access : read-only

RXBNEF : Read data register not empty
bits : 5 - 5 (1 bit)
access : read-write

TXCF : Transmission complete
bits : 6 - 6 (1 bit)
access : read-write

TXBEF : Transmit data register empty
bits : 7 - 7 (1 bit)
access : read-only


CTRL1

Control register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIE PSEL PEN WMS DBL UARTDIS TDB8 RDB8

PIE : UARTx Parity Interrupt Enable mask
bits : 0 - 0 (1 bit)

PSEL : UARTx Parity Selection
bits : 1 - 1 (1 bit)

PEN : Parity Control Enable mask
bits : 2 - 2 (1 bit)

WMS : Wake-up method mask
bits : 3 - 3 (1 bit)

DBL : Word length mask
bits : 4 - 4 (1 bit)

UARTDIS : UARTx Disable (for low power consumption)
bits : 5 - 5 (1 bit)

TDB8 : Transmit data bit 8
bits : 6 - 6 (1 bit)

RDB8 : Receive Data bit 8
bits : 7 - 7 (1 bit)


CTRL2

Control register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBRK RMM RXEN TXEN IDLEIE RXIE TXCIE TXIE

TXBRK : TXBRK
bits : 0 - 0 (1 bit)

RMM : RMM
bits : 1 - 1 (1 bit)

RXEN : RXEN
bits : 2 - 2 (1 bit)

TXEN : TXEN
bits : 3 - 3 (1 bit)

IDLEIE : IDLEIE
bits : 4 - 4 (1 bit)

RXIE : RXIE
bits : 5 - 5 (1 bit)

TXCIE : TXCIE
bits : 6 - 6 (1 bit)

TXIE : TXIE
bits : 7 - 7 (1 bit)


CTRL3

Control register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBCP CLKPHA CLKPOL CLKEN SBS LINEN

LBCP : LBCP
bits : 0 - 0 (1 bit)

CLKPHA : CLKPHA
bits : 1 - 1 (1 bit)

CLKPOL : CLKPOL
bits : 2 - 2 (1 bit)

CLKEN : CLKEN
bits : 3 - 3 (1 bit)

SBS : SBS
bits : 4 - 4 (1 bit)

LINEN : LINEN
bits : 5 - 5 (1 bit)


CTRL4

Control register 4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL4 CTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR LMBDF LMBDL LMBDIE

ADDR : ADDR
bits : 0 - 0 (1 bit)

LMBDF : LMBDF
bits : 1 - 1 (1 bit)

LMBDL : LMBDL
bits : 2 - 2 (1 bit)

LMBDIE : LMBDIE
bits : 3 - 3 (1 bit)


CTRL5

Control register 5
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL5 CTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRDAEN ILPM HDMEN NACKEN SMEN

IRDAEN : IRDAEN
bits : 1 - 1 (1 bit)

ILPM : ILPM
bits : 2 - 2 (1 bit)

HDMEN : HDMEN
bits : 3 - 3 (1 bit)

NACKEN : NACKEN
bits : 4 - 4 (1 bit)

SMEN : SMEN
bits : 5 - 5 (1 bit)


GTS

Guard time and register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTS GTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GTS

GTS : GTS
bits : 8 - 15 (8 bit)


DIV

UART1 prescaler register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : DIV
bits : 8 - 15 (8 bit)


SW

UART2/USART3 switch register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW SW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW

SW : SW
bits : 0 - 0 (1 bit)


IOSW2

UART3 IO switch register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOSW2 IOSW2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW

SW : SW
bits : 0 - 0 (1 bit)


DATA

Data register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data value
bits : 0 - 8 (9 bit)


BR1

Baud rate register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR1 BR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV11_4

DIV11_4 : LSB mantissa of UARTxDIV [7:0] mask
bits : 0 - 7 (8 bit)


BR0

Baud rate register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR0 BR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV3_0 DIV15_12

DIV3_0 : Fraction bits of UARTxDIV [3:0] mask
bits : 0 - 3 (4 bit)

DIV15_12 : MSB mantissa of UARTxDIV [15:12] mask
bits : 4 - 7 (4 bit)



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