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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Counter Enable mask.
bits : 0 - 0 (1 bit)
NGUE : Update DIsable mask.
bits : 1 - 1 (1 bit)
UES : Update Request Source mask.
bits : 2 - 2 (1 bit)
SPMEN : One Pulse Mode mask.
bits : 3 - 3 (1 bit)
CNTDIR : Direction mask.
bits : 4 - 4 (1 bit)
CNTMODE : Center-aligned Mode Selection mask.
bits : 5 - 6 (2 bit)
ARBEN : Auto-Reload Preload Enable mask.
bits : 7 - 7 (1 bit)
interrupt enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIE : Update Interrupt Enable mask.
bits : 0 - 0 (1 bit)
CH1CCIE : Capture/Compare 1 Interrupt Enable mask.
bits : 1 - 1 (1 bit)
CH2CCIE : Capture/Compare 2 Interrupt Enable mask.
bits : 2 - 2 (1 bit)
CH3CCIE : Capture/Compare 3 Interrupt Enable mask.
bits : 3 - 3 (1 bit)
CH4CCIE : Capture/Compare 4 Interrupt Enable mask.
bits : 4 - 4 (1 bit)
CCUIE : Commutation Interrupt Enable mask.
bits : 5 - 5 (1 bit)
TRGIE : Trigger Interrupt Enable mask.
bits : 6 - 6 (1 bit)
BRKIE : Break Interrupt Enable mask.
bits : 7 - 7 (1 bit)
status register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIF : Update Interrupt Flag mask.
bits : 0 - 0 (1 bit)
CH1CCIF : Capture/Compare 1 Interrupt Flag mask.
bits : 1 - 1 (1 bit)
CH2CCIF : Capture/Compare 2 Interrupt Flag mask.
bits : 2 - 2 (1 bit)
CH3CCIF : Capture/Compare 3 Interrupt Flag mask.
bits : 3 - 3 (1 bit)
CH4CCIF : Capture/Compare 4 Interrupt Flag mask.
bits : 4 - 4 (1 bit)
CCUIF : Commutation Interrupt Flag mask.
bits : 5 - 5 (1 bit)
TRGIF : Trigger Interrupt Flag mask.
bits : 6 - 6 (1 bit)
BRKIF : Break Interrupt Flag mask.
bits : 7 - 7 (1 bit)
status register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1RCF : Capture/Compare 1 Overcapture Flag mask.
bits : 1 - 1 (1 bit)
CH2RCF : Capture/Compare 2 Overcapture Flag mask.
bits : 2 - 2 (1 bit)
CH3RCF : Capture/Compare 3 Overcapture Flag mask.
bits : 3 - 3 (1 bit)
CH4RCF : Capture/Compare 4 Overcapture Flag mask.
bits : 4 - 4 (1 bit)
event generation register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UEG : Update Generation mask.
bits : 0 - 0 (1 bit)
CH1CCG : Capture/Compare 1 Generation mask.
bits : 1 - 1 (1 bit)
CH2CCG : Capture/Compare 2 Generation mask.
bits : 2 - 2 (1 bit)
CH3CCG : Capture/Compare 3 Generation mask.
bits : 3 - 3 (1 bit)
CH4CCG : Capture/Compare 4 Generation mask.
bits : 4 - 4 (1 bit)
CCUEG : Capture/Compare Control Update Generation mask.
bits : 5 - 5 (1 bit)
TEG : Trigger Generation mask.
bits : 6 - 6 (1 bit)
BEG : Break Generation mask.
bits : 7 - 7 (1 bit)
CC mode register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
OCFEN : Output Compare 1 Fast Enable mask.
bits : 2 - 2 (1 bit)
OCBEN : Output Compare 1 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 1 Mode mask.
bits : 4 - 6 (3 bit)
OCCEN : Input Capture 1 Filter mask.
bits : 7 - 7 (1 bit)
IC mode register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH1OC
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
ICD : ICD
bits : 2 - 3 (2 bit)
ICFC : ICFC
bits : 4 - 7 (4 bit)
CC mode register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 2 Selection mask.
bits : 0 - 1 (2 bit)
OCFEN : Output Compare 2 Fast Enable mask.
bits : 2 - 2 (1 bit)
OCBEN : Output Compare 2 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 2 Mode mask.
bits : 4 - 6 (3 bit)
OCCEN : Input Capture 2 Filter mask.
bits : 7 - 7 (1 bit)
IC mode register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH2OC
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
ICD : ICD
bits : 2 - 3 (2 bit)
ICFC : ICFC
bits : 4 - 7 (4 bit)
CC mode register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 3 Selection mask.
bits : 0 - 1 (2 bit)
OCFEN : Output Compare 3 Fast Enable mask.
bits : 2 - 2 (1 bit)
OCBEN : Output Compare 3 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 3 Mode mask.
bits : 4 - 6 (3 bit)
OCCEN : Input Capture 3 Filter mask.
bits : 7 - 7 (1 bit)
IC mode register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH3OC
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
ICD : ICD
bits : 2 - 3 (2 bit)
ICFC : ICFC
bits : 4 - 7 (4 bit)
CC mode register 4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 4 Selection mask.
bits : 0 - 1 (2 bit)
OCFEN : Output Compare 4 Fast Enable mask.
bits : 2 - 2 (1 bit)
OCBEN : Output Compare 4 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 4 Mode mask.
bits : 4 - 6 (3 bit)
OCCEN : Input Capture 4 Filter mask.
bits : 7 - 7 (1 bit)
IC mode register 4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH4OC
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
ICD : ICD
bits : 2 - 3 (2 bit)
ICFC : ICFC
bits : 4 - 7 (4 bit)
CC enable register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1CCEN : Capture/Compare 1 output enable mask.
bits : 0 - 0 (1 bit)
CH1CCP : Capture/Compare 1 output Polarity mask.
bits : 1 - 1 (1 bit)
CH1OCNEN : Capture/Compare 1 Complementary output enable mask.
bits : 2 - 2 (1 bit)
CH1OCNP : Capture/Compare 1 Complementary output Polarity mask.
bits : 3 - 3 (1 bit)
CH2CCEN : Capture/Compare 2 output enable mask.
bits : 4 - 4 (1 bit)
CH2CCP : Capture/Compare 2 output Polarity mask.
bits : 5 - 5 (1 bit)
CH2OCNEN : Capture/Compare 2 Complementary output enable mask.
bits : 6 - 6 (1 bit)
CH2OCNP : Capture/Compare 2 Complementary output Polarity mask.
bits : 7 - 7 (1 bit)
CC enable register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3CCEN : Capture/Compare 3 output enable mask.
bits : 0 - 0 (1 bit)
CH3CCP : Capture/Compare 3 output Polarity mask.
bits : 1 - 1 (1 bit)
CH4CCEN : Capture/Compare 3 Complementary output enable mask.
bits : 2 - 2 (1 bit)
CH4CCP : Capture/Compare 3 Complementary output Polarity mask.
bits : 3 - 3 (1 bit)
counter high
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value (MSB) mask.
bits : 0 - 7 (8 bit)
counter low
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value (LSB) mask.
bits : 0 - 7 (8 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBEN : MMS Selection mask.
bits : 0 - 0 (1 bit)
CCUS : Capture/Compare Control Update Selection mask.
bits : 2 - 2 (1 bit)
MMFC : Capture/Compare Preloaded Control mask.
bits : 4 - 6 (3 bit)
prescaler high
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Prescaler Value (MSB) mask.
bits : 0 - 7 (8 bit)
prescaler low
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Prescaler Value (LSB) mask.
bits : 0 - 7 (8 bit)
auto-reload register high
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Autoreload Value (MSB) mask.
bits : 0 - 7 (8 bit)
auto-reload register low
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Autoreload Value (LSB) mask.
bits : 0 - 7 (8 bit)
Repetition Counter register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPCNT : Repetition Counter Value mask.
bits : 0 - 7 (8 bit)
capture/compare register 1 high
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 1 Value (MSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 1 low
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 1 Value (LSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 2 high
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 2 Value (MSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 2 low
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 2 Value (LSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 3 high
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 3 Value (MSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 3 low
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 3 Value (LSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 4 high
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 4 Value (MSB) mask.
bits : 0 - 7 (8 bit)
capture/compare register 4 low
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 4 Value (LSB) mask.
bits : 0 - 7 (8 bit)
Break Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROTCFG : Lock Configuration mask.
bits : 0 - 1 (2 bit)
IMOS : Off-State Selection for Idle mode mask.
bits : 2 - 2 (1 bit)
RMOS : Off-State Selection for Run mode mask.
bits : 3 - 3 (1 bit)
BRKEN : Break Enable mask.
bits : 4 - 4 (1 bit)
BRKPOL : Break Polarity mask.
bits : 5 - 5 (1 bit)
AOEN : Automatic Output Enable mask.
bits : 6 - 6 (1 bit)
WOEN : Main Output Enable mask.
bits : 7 - 7 (1 bit)
dead-time register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DT : Dead-Time Generator set-up mask.
bits : 0 - 7 (8 bit)
Output idle register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1ISO : Output Idle state 1 (OC1 output) mask.
bits : 0 - 0 (1 bit)
CH1NISO : Output Idle state 1 (OC1N output) mask.
bits : 1 - 1 (1 bit)
CH2ISO : Output Idle state 2 (OC2 output) mask.
bits : 2 - 2 (1 bit)
CH2NISO : Output Idle state 2 (OC2N output) mask.
bits : 3 - 3 (1 bit)
CH3ISO : Output Idle state 3 (OC3 output) mask.
bits : 4 - 4 (1 bit)
CH3NISO : Output Idle state 3 (OC3N output) mask.
bits : 5 - 5 (1 bit)
CH4ISO : Output Idle state 4 (OC4 output) mask.
bits : 6 - 6 (1 bit)
CH4NISO : Output Idle state 4 (OC4N output) mask.
bits : 7 - 7 (1 bit)
Synchro mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMFC : Master/Slave Mode mask.
bits : 0 - 2 (3 bit)
ITC : Trigger Selection mask.
bits : 4 - 6 (3 bit)
MSMEN : Slave Mode Selection mask.
bits : 7 - 7 (1 bit)
Timer1A Channel enable register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1 : CH1
bits : 0 - 0 (1 bit)
CH2 : CH2
bits : 1 - 1 (1 bit)
CH3 : CH3
bits : 2 - 2 (1 bit)
CH4 : CH4
bits : 3 - 3 (1 bit)
external trigger register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETFC : External Trigger Filter mask.
bits : 0 - 3 (4 bit)
ETDC : External Trigger Prescaler mask.
bits : 4 - 5 (2 bit)
ECM2EN : External Clock mask.
bits : 6 - 6 (1 bit)
ETPC : External Trigger Polarity mask.
bits : 7 - 7 (1 bit)
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