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TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL1

INTCTRL

STS1

STS2

SCEG

CH1OC

CH1IC

CH2OC

CH2IC

CH3OC

CH3IC

CH4OC

CH4IC

CHCTRL1

CHCTRL2

CNT1

CNT0

CTRL2

DIV1

DIV0

AUTORLD1

AUTORLD0

REPCNT

CH1CC1

CH1CC0

CH2CC1

CH2CC0

CH3CC1

CH3CC0

CH4CC1

CH4CC0

BRKCTRL

DTS

ISO

SMC

CHEN

ETC


CTRL1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN NGUE UES SPMEN CNTDIR CNTMODE ARBEN

CNTEN : Counter Enable mask.
bits : 0 - 0 (1 bit)

NGUE : Update DIsable mask.
bits : 1 - 1 (1 bit)

UES : Update Request Source mask.
bits : 2 - 2 (1 bit)

SPMEN : One Pulse Mode mask.
bits : 3 - 3 (1 bit)

CNTDIR : Direction mask.
bits : 4 - 4 (1 bit)

CNTMODE : Center-aligned Mode Selection mask.
bits : 5 - 6 (2 bit)

ARBEN : Auto-Reload Preload Enable mask.
bits : 7 - 7 (1 bit)


INTCTRL

interrupt enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCTRL INTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDIE CH1CCIE CH2CCIE CH3CCIE CH4CCIE CCUIE TRGIE BRKIE

UDIE : Update Interrupt Enable mask.
bits : 0 - 0 (1 bit)

CH1CCIE : Capture/Compare 1 Interrupt Enable mask.
bits : 1 - 1 (1 bit)

CH2CCIE : Capture/Compare 2 Interrupt Enable mask.
bits : 2 - 2 (1 bit)

CH3CCIE : Capture/Compare 3 Interrupt Enable mask.
bits : 3 - 3 (1 bit)

CH4CCIE : Capture/Compare 4 Interrupt Enable mask.
bits : 4 - 4 (1 bit)

CCUIE : Commutation Interrupt Enable mask.
bits : 5 - 5 (1 bit)

TRGIE : Trigger Interrupt Enable mask.
bits : 6 - 6 (1 bit)

BRKIE : Break Interrupt Enable mask.
bits : 7 - 7 (1 bit)


STS1

status register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS1 STS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDIF CH1CCIF CH2CCIF CH3CCIF CH4CCIF CCUIF TRGIF BRKIF

UDIF : Update Interrupt Flag mask.
bits : 0 - 0 (1 bit)

CH1CCIF : Capture/Compare 1 Interrupt Flag mask.
bits : 1 - 1 (1 bit)

CH2CCIF : Capture/Compare 2 Interrupt Flag mask.
bits : 2 - 2 (1 bit)

CH3CCIF : Capture/Compare 3 Interrupt Flag mask.
bits : 3 - 3 (1 bit)

CH4CCIF : Capture/Compare 4 Interrupt Flag mask.
bits : 4 - 4 (1 bit)

CCUIF : Commutation Interrupt Flag mask.
bits : 5 - 5 (1 bit)

TRGIF : Trigger Interrupt Flag mask.
bits : 6 - 6 (1 bit)

BRKIF : Break Interrupt Flag mask.
bits : 7 - 7 (1 bit)


STS2

status register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS2 STS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1RCF CH2RCF CH3RCF CH4RCF

CH1RCF : Capture/Compare 1 Overcapture Flag mask.
bits : 1 - 1 (1 bit)

CH2RCF : Capture/Compare 2 Overcapture Flag mask.
bits : 2 - 2 (1 bit)

CH3RCF : Capture/Compare 3 Overcapture Flag mask.
bits : 3 - 3 (1 bit)

CH4RCF : Capture/Compare 4 Overcapture Flag mask.
bits : 4 - 4 (1 bit)


SCEG

event generation register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCEG SCEG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEG CH1CCG CH2CCG CH3CCG CH4CCG CCUEG TEG BEG

UEG : Update Generation mask.
bits : 0 - 0 (1 bit)

CH1CCG : Capture/Compare 1 Generation mask.
bits : 1 - 1 (1 bit)

CH2CCG : Capture/Compare 2 Generation mask.
bits : 2 - 2 (1 bit)

CH3CCG : Capture/Compare 3 Generation mask.
bits : 3 - 3 (1 bit)

CH4CCG : Capture/Compare 4 Generation mask.
bits : 4 - 4 (1 bit)

CCUEG : Capture/Compare Control Update Generation mask.
bits : 5 - 5 (1 bit)

TEG : Trigger Generation mask.
bits : 6 - 6 (1 bit)

BEG : Break Generation mask.
bits : 7 - 7 (1 bit)


CH1OC

CC mode register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1OC CH1OC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCFEN OCBEN OCMS OCCEN

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

OCFEN : Output Compare 1 Fast Enable mask.
bits : 2 - 2 (1 bit)

OCBEN : Output Compare 1 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 1 Mode mask.
bits : 4 - 6 (3 bit)

OCCEN : Input Capture 1 Filter mask.
bits : 7 - 7 (1 bit)


CH1IC

IC mode register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH1OC
reset_Mask : 0x0

CH1IC CH1IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

ICD : ICD
bits : 2 - 3 (2 bit)

ICFC : ICFC
bits : 4 - 7 (4 bit)


CH2OC

CC mode register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2OC CH2OC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCFEN OCBEN OCMS OCCEN

MODESEL : Capture/Compare 2 Selection mask.
bits : 0 - 1 (2 bit)

OCFEN : Output Compare 2 Fast Enable mask.
bits : 2 - 2 (1 bit)

OCBEN : Output Compare 2 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 2 Mode mask.
bits : 4 - 6 (3 bit)

OCCEN : Input Capture 2 Filter mask.
bits : 7 - 7 (1 bit)


CH2IC

IC mode register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH2OC
reset_Mask : 0x0

CH2IC CH2IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

ICD : ICD
bits : 2 - 3 (2 bit)

ICFC : ICFC
bits : 4 - 7 (4 bit)


CH3OC

CC mode register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3OC CH3OC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCFEN OCBEN OCMS OCCEN

MODESEL : Capture/Compare 3 Selection mask.
bits : 0 - 1 (2 bit)

OCFEN : Output Compare 3 Fast Enable mask.
bits : 2 - 2 (1 bit)

OCBEN : Output Compare 3 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 3 Mode mask.
bits : 4 - 6 (3 bit)

OCCEN : Input Capture 3 Filter mask.
bits : 7 - 7 (1 bit)


CH3IC

IC mode register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH3OC
reset_Mask : 0x0

CH3IC CH3IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

ICD : ICD
bits : 2 - 3 (2 bit)

ICFC : ICFC
bits : 4 - 7 (4 bit)


CH4OC

CC mode register 4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4OC CH4OC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCFEN OCBEN OCMS OCCEN

MODESEL : Capture/Compare 4 Selection mask.
bits : 0 - 1 (2 bit)

OCFEN : Output Compare 4 Fast Enable mask.
bits : 2 - 2 (1 bit)

OCBEN : Output Compare 4 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 4 Mode mask.
bits : 4 - 6 (3 bit)

OCCEN : Input Capture 4 Filter mask.
bits : 7 - 7 (1 bit)


CH4IC

IC mode register 4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH4OC
reset_Mask : 0x0

CH4IC CH4IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

ICD : ICD
bits : 2 - 3 (2 bit)

ICFC : ICFC
bits : 4 - 7 (4 bit)


CHCTRL1

CC enable register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRL1 CHCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1CCEN CH1CCP CH1OCNEN CH1OCNP CH2CCEN CH2CCP CH2OCNEN CH2OCNP

CH1CCEN : Capture/Compare 1 output enable mask.
bits : 0 - 0 (1 bit)

CH1CCP : Capture/Compare 1 output Polarity mask.
bits : 1 - 1 (1 bit)

CH1OCNEN : Capture/Compare 1 Complementary output enable mask.
bits : 2 - 2 (1 bit)

CH1OCNP : Capture/Compare 1 Complementary output Polarity mask.
bits : 3 - 3 (1 bit)

CH2CCEN : Capture/Compare 2 output enable mask.
bits : 4 - 4 (1 bit)

CH2CCP : Capture/Compare 2 output Polarity mask.
bits : 5 - 5 (1 bit)

CH2OCNEN : Capture/Compare 2 Complementary output enable mask.
bits : 6 - 6 (1 bit)

CH2OCNP : Capture/Compare 2 Complementary output Polarity mask.
bits : 7 - 7 (1 bit)


CHCTRL2

CC enable register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRL2 CHCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3CCEN CH3CCP CH4CCEN CH4CCP

CH3CCEN : Capture/Compare 3 output enable mask.
bits : 0 - 0 (1 bit)

CH3CCP : Capture/Compare 3 output Polarity mask.
bits : 1 - 1 (1 bit)

CH4CCEN : Capture/Compare 3 Complementary output enable mask.
bits : 2 - 2 (1 bit)

CH4CCP : Capture/Compare 3 Complementary output Polarity mask.
bits : 3 - 3 (1 bit)


CNT1

counter high
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT1 CNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value (MSB) mask.
bits : 0 - 7 (8 bit)


CNT0

counter low
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT0 CNT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value (LSB) mask.
bits : 0 - 7 (8 bit)


CTRL2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBEN CCUS MMFC

CCBEN : MMS Selection mask.
bits : 0 - 0 (1 bit)

CCUS : Capture/Compare Control Update Selection mask.
bits : 2 - 2 (1 bit)

MMFC : Capture/Compare Preloaded Control mask.
bits : 4 - 6 (3 bit)


DIV1

prescaler high
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV1 DIV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Prescaler Value (MSB) mask.
bits : 0 - 7 (8 bit)


DIV0

prescaler low
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV0 DIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Prescaler Value (LSB) mask.
bits : 0 - 7 (8 bit)


AUTORLD1

auto-reload register high
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTORLD1 AUTORLD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : Autoreload Value (MSB) mask.
bits : 0 - 7 (8 bit)


AUTORLD0

auto-reload register low
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTORLD0 AUTORLD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : Autoreload Value (LSB) mask.
bits : 0 - 7 (8 bit)


REPCNT

Repetition Counter register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REPCNT REPCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REPCNT

REPCNT : Repetition Counter Value mask.
bits : 0 - 7 (8 bit)


CH1CC1

capture/compare register 1 high
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CC1 CH1CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 1 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH1CC0

capture/compare register 1 low
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CC0 CH1CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 1 Value (LSB) mask.
bits : 0 - 7 (8 bit)


CH2CC1

capture/compare register 2 high
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CC1 CH2CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 2 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH2CC0

capture/compare register 2 low
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CC0 CH2CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 2 Value (LSB) mask.
bits : 0 - 7 (8 bit)


CH3CC1

capture/compare register 3 high
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CC1 CH3CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 3 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH3CC0

capture/compare register 3 low
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CC0 CH3CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 3 Value (LSB) mask.
bits : 0 - 7 (8 bit)


CH4CC1

capture/compare register 4 high
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CC1 CH4CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 4 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH4CC0

capture/compare register 4 low
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CC0 CH4CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 4 Value (LSB) mask.
bits : 0 - 7 (8 bit)


BRKCTRL

Break Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKCTRL BRKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTCFG IMOS RMOS BRKEN BRKPOL AOEN WOEN

PROTCFG : Lock Configuration mask.
bits : 0 - 1 (2 bit)

IMOS : Off-State Selection for Idle mode mask.
bits : 2 - 2 (1 bit)

RMOS : Off-State Selection for Run mode mask.
bits : 3 - 3 (1 bit)

BRKEN : Break Enable mask.
bits : 4 - 4 (1 bit)

BRKPOL : Break Polarity mask.
bits : 5 - 5 (1 bit)

AOEN : Automatic Output Enable mask.
bits : 6 - 6 (1 bit)

WOEN : Main Output Enable mask.
bits : 7 - 7 (1 bit)


DTS

dead-time register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS DTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT

DT : Dead-Time Generator set-up mask.
bits : 0 - 7 (8 bit)


ISO

Output idle register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISO ISO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1ISO CH1NISO CH2ISO CH2NISO CH3ISO CH3NISO CH4ISO CH4NISO

CH1ISO : Output Idle state 1 (OC1 output) mask.
bits : 0 - 0 (1 bit)

CH1NISO : Output Idle state 1 (OC1N output) mask.
bits : 1 - 1 (1 bit)

CH2ISO : Output Idle state 2 (OC2 output) mask.
bits : 2 - 2 (1 bit)

CH2NISO : Output Idle state 2 (OC2N output) mask.
bits : 3 - 3 (1 bit)

CH3ISO : Output Idle state 3 (OC3 output) mask.
bits : 4 - 4 (1 bit)

CH3NISO : Output Idle state 3 (OC3N output) mask.
bits : 5 - 5 (1 bit)

CH4ISO : Output Idle state 4 (OC4 output) mask.
bits : 6 - 6 (1 bit)

CH4NISO : Output Idle state 4 (OC4N output) mask.
bits : 7 - 7 (1 bit)


SMC

Synchro mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMC SMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMFC ITC MSMEN

SMFC : Master/Slave Mode mask.
bits : 0 - 2 (3 bit)

ITC : Trigger Selection mask.
bits : 4 - 6 (3 bit)

MSMEN : Slave Mode Selection mask.
bits : 7 - 7 (1 bit)


CHEN

Timer1A Channel enable register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEN CHEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1 CH2 CH3 CH4

CH1 : CH1
bits : 0 - 0 (1 bit)

CH2 : CH2
bits : 1 - 1 (1 bit)

CH3 : CH3
bits : 2 - 2 (1 bit)

CH4 : CH4
bits : 3 - 3 (1 bit)


ETC

external trigger register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETC ETC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETFC ETDC ECM2EN ETPC

ETFC : External Trigger Filter mask.
bits : 0 - 3 (4 bit)

ETDC : External Trigger Prescaler mask.
bits : 4 - 5 (2 bit)

ECM2EN : External Clock mask.
bits : 6 - 6 (1 bit)

ETPC : External Trigger Polarity mask.
bits : 7 - 7 (1 bit)



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