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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Counter Enable mask.
bits : 0 - 0 (1 bit)
NGUE : Update DIsable mask.
bits : 1 - 1 (1 bit)
UES : Update Request Source mask.
bits : 2 - 2 (1 bit)
SPMEN : One Pulse Mode mask.
bits : 3 - 3 (1 bit)
ARBEN : Auto-Reload Preload Enable mask.
bits : 7 - 7 (1 bit)
status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIF : Update Interrupt Flag mask.
bits : 0 - 0 (1 bit)
CH1CCIF : Capture/Compare 1 Interrupt Flag mask.
bits : 1 - 1 (1 bit)
CH2CCIF : Capture/Compare 2 Interrupt Flag mask.
bits : 2 - 2 (1 bit)
CH3CCIF : Capture/Compare 3 Interrupt Flag mask.
bits : 3 - 3 (1 bit)
TRGIF : Trigger Interrupt Flag mask.
bits : 6 - 6 (1 bit)
status register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1RCF : Capture/Compare 1 Overcapture Flag mask.
bits : 1 - 1 (1 bit)
CH2RCF : Capture/Compare 2 Overcapture Flag mask.
bits : 2 - 2 (1 bit)
CH3RCF : Capture/Compare 3 Overcapture Flag mask.
bits : 3 - 3 (1 bit)
event generation register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UEG : Update Generation mask.
bits : 0 - 0 (1 bit)
CH1CCG : Capture/Compare 1 Generation mask.
bits : 1 - 1 (1 bit)
CH2CCG : Capture/Compare 2 Generation mask.
bits : 2 - 2 (1 bit)
CH3CCG : Capture/Compare 3 Generation mask.
bits : 3 - 3 (1 bit)
TEG : Trigger Generation mask.
bits : 6 - 6 (1 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
OCBEN : Output Compare 1 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 1 Mode mask.
bits : 4 - 6 (3 bit)
capture/compare mode register 1 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH1OC
reset_Mask : 0x0
MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)
ICD : Input capture 1 prescaler
bits : 2 - 3 (2 bit)
ICFC : Input capture 1 filter
bits : 4 - 7 (4 bit)
capture/compare mode register 2 (output mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 2 Selection mask.
bits : 0 - 1 (2 bit)
OCBEN : Output Compare 2 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 2 Mode mask.
bits : 4 - 6 (3 bit)
capture/compare mode register 2 (input mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH2OC
reset_Mask : 0x0
MODESEL : Capture/Compare 2 Selection mask.
bits : 0 - 1 (2 bit)
ICD : Input capture 2 prescaler
bits : 2 - 3 (2 bit)
ICFC : Input capture 2 filter
bits : 4 - 7 (4 bit)
capture/compare mode register 3 (output mode)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODESEL : Capture/Compare 3 Selection mask.
bits : 0 - 1 (2 bit)
OCBEN : Output Compare 3 Preload Enable mask.
bits : 3 - 3 (1 bit)
OCMS : Output Compare 3 Mode mask.
bits : 4 - 6 (3 bit)
capture/compare mode register 3 (input mode)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH3OC
reset_Mask : 0x0
MODESEL : Capture/Compare 3 Selection mask.
bits : 0 - 1 (2 bit)
ICD : Input capture 3 prescaler
bits : 2 - 3 (2 bit)
ICFC : Input capture 3 filter
bits : 4 - 7 (4 bit)
Channel control register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1CCEN : Capture/Compare 1 output enable mask.
bits : 0 - 0 (1 bit)
CH1CCP : Capture/Compare 1 output Polarity mask.
bits : 1 - 1 (1 bit)
CH2CCEN : Capture/Compare 2 output enable mask.
bits : 4 - 4 (1 bit)
CH2CCP : Capture/Compare 2 output Polarity mask.
bits : 5 - 5 (1 bit)
Channel control register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3CCEN : Capture/Compare 3 output enable mask.
bits : 0 - 0 (1 bit)
CH3CCP : Capture/Compare 3 output Polarity mask.
bits : 1 - 1 (1 bit)
Count register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value (MSB) mask.
bits : 0 - 7 (8 bit)
Count register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value (LSB) mask.
bits : 0 - 7 (8 bit)
divider register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Prescaler Value mask.
bits : 0 - 3 (4 bit)
Auto reload register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Autoreload Value (MSB) mask.
bits : 0 - 7 (8 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMFC : Capture/Compare Preloaded Control mask.
bits : 4 - 6 (3 bit)
Auto reload register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : Autoreload Value (LSB) mask.
bits : 0 - 7 (8 bit)
channel 1 compare/capture register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 1 Value (MSB) mask.
bits : 0 - 7 (8 bit)
channel 1 compare/capture register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 1 Value (LSB) mask.
bits : 0 - 7 (8 bit)
channel 2 compare/capture register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 2 Value (MSB) mask.
bits : 0 - 7 (8 bit)
channel 2 compare/capture register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 2 Value (LSB) mask.
bits : 0 - 7 (8 bit)
channel 3 compare/capture register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 3 Value (MSB) mask.
bits : 0 - 7 (8 bit)
channel 3 compare/capture register 0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Capture/Compare 3 Value (LSB) mask.
bits : 0 - 7 (8 bit)
Synchro mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMFC : Master/Slave Mode mask.
bits : 0 - 2 (3 bit)
ITC : Trigger Selection mask.
bits : 4 - 6 (3 bit)
MSMEN : Slave Mode Selection mask.
bits : 7 - 7 (1 bit)
interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIE : Update Interrupt Enable mask.
bits : 0 - 0 (1 bit)
CH1CCIE : Capture/Compare 1 Interrupt Enable mask.
bits : 1 - 1 (1 bit)
CH2CCIE : Capture/Compare 2 Interrupt Enable mask.
bits : 2 - 2 (1 bit)
CH3CCIE : Capture/Compare 3 Interrupt Enable mask.
bits : 3 - 3 (1 bit)
TRGIE : Trigger Interrupt Enable mask.
bits : 6 - 6 (1 bit)
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