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TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL1

STS1

STS2

SCEG

CH1CCM (CH1OC)

CH1CCM (CH1IC)

CH2CCM (CH2OC)

CH2CCM (CH2IC)

CH3CCM (CH3OC)

CH3CCM (CH3IC)

CHCTRL1

CHCTRL2

CNT1

CNT0

DIV

AUTORLD1

CTRL2

AUTORLD0

CH1CC1

CH1CC0

CH2CC1

CH2CC0

CH3CC1

CH3CC0

SMC

INTCTRL


CTRL1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN NGUE UES SPMEN ARBEN

CNTEN : Counter Enable mask.
bits : 0 - 0 (1 bit)

NGUE : Update DIsable mask.
bits : 1 - 1 (1 bit)

UES : Update Request Source mask.
bits : 2 - 2 (1 bit)

SPMEN : One Pulse Mode mask.
bits : 3 - 3 (1 bit)

ARBEN : Auto-Reload Preload Enable mask.
bits : 7 - 7 (1 bit)


STS1

status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS1 STS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDIF CH1CCIF CH2CCIF CH3CCIF TRGIF

UDIF : Update Interrupt Flag mask.
bits : 0 - 0 (1 bit)

CH1CCIF : Capture/Compare 1 Interrupt Flag mask.
bits : 1 - 1 (1 bit)

CH2CCIF : Capture/Compare 2 Interrupt Flag mask.
bits : 2 - 2 (1 bit)

CH3CCIF : Capture/Compare 3 Interrupt Flag mask.
bits : 3 - 3 (1 bit)

TRGIF : Trigger Interrupt Flag mask.
bits : 6 - 6 (1 bit)


STS2

status register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS2 STS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1RCF CH2RCF CH3RCF

CH1RCF : Capture/Compare 1 Overcapture Flag mask.
bits : 1 - 1 (1 bit)

CH2RCF : Capture/Compare 2 Overcapture Flag mask.
bits : 2 - 2 (1 bit)

CH3RCF : Capture/Compare 3 Overcapture Flag mask.
bits : 3 - 3 (1 bit)


SCEG

event generation register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCEG SCEG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEG CH1CCG CH2CCG CH3CCG TEG

UEG : Update Generation mask.
bits : 0 - 0 (1 bit)

CH1CCG : Capture/Compare 1 Generation mask.
bits : 1 - 1 (1 bit)

CH2CCG : Capture/Compare 2 Generation mask.
bits : 2 - 2 (1 bit)

CH3CCG : Capture/Compare 3 Generation mask.
bits : 3 - 3 (1 bit)

TEG : Trigger Generation mask.
bits : 6 - 6 (1 bit)


CH1CCM (CH1OC)

capture/compare mode register 1 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CCM CH1CCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCBEN OCMS

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

OCBEN : Output Compare 1 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 1 Mode mask.
bits : 4 - 6 (3 bit)


CH1CCM (CH1IC)

capture/compare mode register 1 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH1OC
reset_Mask : 0x0

CH1CCM CH1CCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 1 Selection mask.
bits : 0 - 1 (2 bit)

ICD : Input capture 1 prescaler
bits : 2 - 3 (2 bit)

ICFC : Input capture 1 filter
bits : 4 - 7 (4 bit)


CH2CCM (CH2OC)

capture/compare mode register 2 (output mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CCM CH2CCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCBEN OCMS

MODESEL : Capture/Compare 2 Selection mask.
bits : 0 - 1 (2 bit)

OCBEN : Output Compare 2 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 2 Mode mask.
bits : 4 - 6 (3 bit)


CH2CCM (CH2IC)

capture/compare mode register 2 (input mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH2OC
reset_Mask : 0x0

CH2CCM CH2CCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 2 Selection mask.
bits : 0 - 1 (2 bit)

ICD : Input capture 2 prescaler
bits : 2 - 3 (2 bit)

ICFC : Input capture 2 filter
bits : 4 - 7 (4 bit)


CH3CCM (CH3OC)

capture/compare mode register 3 (output mode)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CCM CH3CCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL OCBEN OCMS

MODESEL : Capture/Compare 3 Selection mask.
bits : 0 - 1 (2 bit)

OCBEN : Output Compare 3 Preload Enable mask.
bits : 3 - 3 (1 bit)

OCMS : Output Compare 3 Mode mask.
bits : 4 - 6 (3 bit)


CH3CCM (CH3IC)

capture/compare mode register 3 (input mode)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CH3OC
reset_Mask : 0x0

CH3CCM CH3CCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL ICD ICFC

MODESEL : Capture/Compare 3 Selection mask.
bits : 0 - 1 (2 bit)

ICD : Input capture 3 prescaler
bits : 2 - 3 (2 bit)

ICFC : Input capture 3 filter
bits : 4 - 7 (4 bit)


CHCTRL1

Channel control register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRL1 CHCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1CCEN CH1CCP CH2CCEN CH2CCP

CH1CCEN : Capture/Compare 1 output enable mask.
bits : 0 - 0 (1 bit)

CH1CCP : Capture/Compare 1 output Polarity mask.
bits : 1 - 1 (1 bit)

CH2CCEN : Capture/Compare 2 output enable mask.
bits : 4 - 4 (1 bit)

CH2CCP : Capture/Compare 2 output Polarity mask.
bits : 5 - 5 (1 bit)


CHCTRL2

Channel control register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRL2 CHCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3CCEN CH3CCP

CH3CCEN : Capture/Compare 3 output enable mask.
bits : 0 - 0 (1 bit)

CH3CCP : Capture/Compare 3 output Polarity mask.
bits : 1 - 1 (1 bit)


CNT1

Count register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT1 CNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value (MSB) mask.
bits : 0 - 7 (8 bit)


CNT0

Count register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT0 CNT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value (LSB) mask.
bits : 0 - 7 (8 bit)


DIV

divider register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Prescaler Value mask.
bits : 0 - 3 (4 bit)


AUTORLD1

Auto reload register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTORLD1 AUTORLD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : Autoreload Value (MSB) mask.
bits : 0 - 7 (8 bit)


CTRL2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMFC

MMFC : Capture/Compare Preloaded Control mask.
bits : 4 - 6 (3 bit)


AUTORLD0

Auto reload register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTORLD0 AUTORLD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : Autoreload Value (LSB) mask.
bits : 0 - 7 (8 bit)


CH1CC1

channel 1 compare/capture register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CC1 CH1CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 1 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH1CC0

channel 1 compare/capture register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CC0 CH1CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 1 Value (LSB) mask.
bits : 0 - 7 (8 bit)


CH2CC1

channel 2 compare/capture register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CC1 CH2CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 2 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH2CC0

channel 2 compare/capture register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CC0 CH2CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 2 Value (LSB) mask.
bits : 0 - 7 (8 bit)


CH3CC1

channel 3 compare/capture register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CC1 CH3CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 3 Value (MSB) mask.
bits : 0 - 7 (8 bit)


CH3CC0

channel 3 compare/capture register 0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CC0 CH3CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Capture/Compare 3 Value (LSB) mask.
bits : 0 - 7 (8 bit)


SMC

Synchro mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMC SMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMFC ITC MSMEN

SMFC : Master/Slave Mode mask.
bits : 0 - 2 (3 bit)

ITC : Trigger Selection mask.
bits : 4 - 6 (3 bit)

MSMEN : Slave Mode Selection mask.
bits : 7 - 7 (1 bit)


INTCTRL

interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCTRL INTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDIE CH1CCIE CH2CCIE CH3CCIE TRGIE

UDIE : Update Interrupt Enable mask.
bits : 0 - 0 (1 bit)

CH1CCIE : Capture/Compare 1 Interrupt Enable mask.
bits : 1 - 1 (1 bit)

CH2CCIE : Capture/Compare 2 Interrupt Enable mask.
bits : 2 - 2 (1 bit)

CH3CCIE : Capture/Compare 3 Interrupt Enable mask.
bits : 3 - 3 (1 bit)

TRGIE : Trigger Interrupt Enable mask.
bits : 6 - 6 (1 bit)



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