\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Counter Enable mask.
bits : 0 - 0 (1 bit)
NGUE : Update DIsable mask.
bits : 1 - 1 (1 bit)
UES : Update Request Source mask.
bits : 2 - 2 (1 bit)
SPMEN : One Pulse Mode mask.
bits : 3 - 3 (1 bit)
ARBEN : Auto-Reload Preload Enable mask.
bits : 7 - 7 (1 bit)
status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDIF : Update Interrupt Flag mask.
bits : 0 - 0 (1 bit)
TRGIF : Trigger Interrupt Flag mask.
bits : 6 - 6 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UEG : Update Generation mask.
bits : 0 - 0 (1 bit)
TEG : Trigger Generation mask.
bits : 6 - 6 (1 bit)
counter
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value mask.
bits : 0 - 7 (8 bit)
divider register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Prescaler Value mask.
bits : 0 - 2 (3 bit)
auto-reload register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Autoreload Value mask.
bits : 0 - 7 (8 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMFC : Capture/Compare Preloaded Control mask.
bits : 4 - 6 (3 bit)
Synchro mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMFC : Master/Slave Mode mask.
bits : 0 - 2 (3 bit)
ITC : Trigger Selection mask.
bits : 4 - 6 (3 bit)
MSMEN : Slave Mode Selection mask.
bits : 7 - 7 (1 bit)
interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIE : Update Interrupt Enable mask.
bits : 0 - 0 (1 bit)
TRGIE : Trigger Interrupt Enable mask.
bits : 6 - 6 (1 bit)
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