\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Data buffer 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF0 : Regular data 0
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF4 : Regular data 4
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF5 : Regular data 5
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF6 : Regular data 6
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF7 : Regular data 7
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF8 : Regular data 8
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF9 : Regular data 9
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF10 : Regular data 10
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF11 : Regular data 11
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF12 : Regular data 12
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF13 : Regular data 13
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF14 : Regular data 14
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF15 : Regular data 15
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF1 : Regular data 1
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF16 : Regular data 16
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF17 : Regular data 17
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF18 : Regular data 18
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF19 : Regular data 19
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF2 : Regular data 2
bits : 0 - 7 (8 bit)
control/status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : CHSEL
bits : 0 - 3 (4 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
CCIE : CCIE
bits : 5 - 5 (1 bit)
AWDF : Analog watchdog flag
bits : 6 - 6 (1 bit)
CCF : Regular channel end of conversion
bits : 7 - 7 (1 bit)
control register 1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCON : ADCON
bits : 0 - 0 (1 bit)
CCM : CCM
bits : 1 - 1 (1 bit)
DIVSEL : DIVSEL
bits : 4 - 6 (3 bit)
control register 2
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMEN : SMEN
bits : 1 - 1 (1 bit)
DAM : DAM
bits : 3 - 3 (1 bit)
ETS : ETS
bits : 4 - 5 (2 bit)
ETEN : ETEN
bits : 6 - 6 (1 bit)
control register 3
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRF : OVRF
bits : 6 - 6 (1 bit)
DBEN : DBEN
bits : 7 - 7 (1 bit)
high-regular data register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Regular data
bits : 0 - 7 (8 bit)
low-regular data register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Regular data
bits : 0 - 7 (8 bit)
Schmitt trigger disable register high
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STD : Schmitt trigger prohibit high
bits : 0 - 7 (8 bit)
Schmitt trigger disable register low
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STD : Schmitt trigger prohibit low
bits : 0 - 7 (8 bit)
watchdog higher threshold register high
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THRESHOLD : Analog watchdog higher threshold high
bits : 0 - 7 (8 bit)
watchdog higher threshold register low
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THRESHOLD : Analog watchdog higher threshold low
bits : 0 - 7 (8 bit)
watchdog lower threshold register high
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT : Analog watchdog lower threshold high
bits : 0 - 7 (8 bit)
watchdog lower threshold register low
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THRESHOLD : Analog watchdog lower threshold low
bits : 0 - 7 (8 bit)
Watchdog status high register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWDS : Watchdog status register
bits : 0 - 1 (2 bit)
Watchdog status low register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWDS : Watchdog status register
bits : 0 - 7 (8 bit)
Watchdog Control high register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWDEN : Watchdog Control egister
bits : 0 - 1 (2 bit)
Watchdog Control low register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWDEN : Watchdog Control egister
bits : 0 - 7 (8 bit)
Data buffer 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF3 : Regular data 3
bits : 0 - 7 (8 bit)
Control register 4
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISH : DISH
bits : 0 - 0 (1 bit)
GCMP : GCMP
bits : 1 - 1 (1 bit)
DFS : DFS
bits : 2 - 2 (1 bit)
Offset register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : OFFSET
bits : 0 - 7 (8 bit)
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