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RCM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

APB1RST

AHBCLKEN

APB2CLKEN

APB1CLKEN

BD

CSTS

CFG

INT

APB2RST


CTRL

Clock control register (RCM_CTRL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRCEN HIRCRDYF HIRCTRIM HIRCCAL HXTEN HXTRDYF HXTBYP CSSEN PLLEN PLLRDYF

HIRCEN : Internal High Speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HIRCRDYF : Internal High Speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HIRCTRIM : Internal High Speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HIRCCAL : Internal High Speed clock Calibration
bits : 8 - 15 (8 bit)
access : read-only

HXTEN : External High Speed clock enable
bits : 16 - 16 (1 bit)
access : read-write

HXTRDYF : External High Speed clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HXTBYP : External High Speed clock Bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSEN : Clock Security System enable
bits : 19 - 19 (1 bit)
access : read-write

PLLEN : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDYF : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


APB1RST

APB1 peripheral reset register (RCM_APB1RST)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RST APB1RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR2RST TMR3RST TMR4RST TMR5RST TMR6RST TMR7RST WWDTRST SPI2RST SPI3RST USART2RST USART3RST UART4RST UART5RST I2C1RST I2C2RST USBRST CANRST BAKRRST PMURST DACRST

TMR2RST : Timer 2 reset
bits : 0 - 0 (1 bit)

TMR3RST : Timer 3 reset
bits : 1 - 1 (1 bit)

TMR4RST : Timer 4 reset
bits : 2 - 2 (1 bit)

TMR5RST : Timer 5 reset
bits : 3 - 3 (1 bit)

TMR6RST : Timer 6 reset
bits : 4 - 4 (1 bit)

TMR7RST : Timer 7 reset
bits : 5 - 5 (1 bit)

WWDTRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

SPI3RST : SPI3 reset
bits : 15 - 15 (1 bit)

USART2RST : USART 2 reset
bits : 16 - 16 (1 bit)

USART3RST : USART 3 reset
bits : 17 - 17 (1 bit)

UART4RST : UART 4 reset
bits : 18 - 18 (1 bit)

UART5RST : UART 5 reset
bits : 19 - 19 (1 bit)

I2C1RST : I2C1 reset
bits : 20 - 20 (1 bit)

I2C2RST : I2C2 reset
bits : 21 - 21 (1 bit)

USBRST : USB reset
bits : 22 - 22 (1 bit)

CANRST : CAN reset
bits : 24 - 24 (1 bit)

BAKRRST : Bakr interface reset
bits : 26 - 26 (1 bit)

PMURST : Power interface reset
bits : 27 - 27 (1 bit)

DACRST : DAC interface reset
bits : 28 - 28 (1 bit)


AHBCLKEN

AHB clock enable register (RCM_AHBCLKEN)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLKEN AHBCLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1CLKE DMA2CLKE SRAMCLKE FPUCLKE FMCCLKE QSPICLKE CRCCLKE EMMCCLKEN SDIOCLKE

DMA1CLKE : DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2CLKE : DMA2 clock enable
bits : 1 - 1 (1 bit)

SRAMCLKE : SRAM interface clock enable
bits : 2 - 2 (1 bit)

FPUCLKE : FLITF clock enable
bits : 3 - 3 (1 bit)

FMCCLKE : CRC clock enable
bits : 4 - 4 (1 bit)

QSPICLKE :
bits : 5 - 5 (1 bit)

CRCCLKE :
bits : 6 - 6 (1 bit)

EMMCCLKEN : FSMC clock enable
bits : 8 - 8 (1 bit)

SDIOCLKE : SDIO clock enable
bits : 10 - 10 (1 bit)


APB2CLKEN

APB2 clock enable register (RCM_APB2CLKEN)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2CLKEN APB2CLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIOCLKE PACLKE PBCLKE PCCLKE PDCLKE PECLKE PFCLKE PGCLKE ADC1CLKE ADC2CLKE TMR1CLKE SPI1CLKE TMR8CLKE USART1CLKE ADC3CLKE

AFIOCLKE : Alternate function I/O clock enable
bits : 0 - 0 (1 bit)

PACLKE : I/O port A clock enable
bits : 2 - 2 (1 bit)

PBCLKE : I/O port B clock enable
bits : 3 - 3 (1 bit)

PCCLKE : I/O port C clock enable
bits : 4 - 4 (1 bit)

PDCLKE : I/O port D clock enable
bits : 5 - 5 (1 bit)

PECLKE : I/O port E clock enable
bits : 6 - 6 (1 bit)

PFCLKE : I/O port F clock enable
bits : 7 - 7 (1 bit)

PGCLKE : I/O port G clock enable
bits : 8 - 8 (1 bit)

ADC1CLKE : ADC 1 interface clock enable
bits : 9 - 9 (1 bit)

ADC2CLKE : ADC 2 interface clock enable
bits : 10 - 10 (1 bit)

TMR1CLKE : TMR1 Timer clock enable
bits : 11 - 11 (1 bit)

SPI1CLKE : SPI 1 clock enable
bits : 12 - 12 (1 bit)

TMR8CLKE : TMR8 Timer clock enable
bits : 13 - 13 (1 bit)

USART1CLKE : USART1 clock enable
bits : 14 - 14 (1 bit)

ADC3CLKE : ADC3 interface clock enable
bits : 15 - 15 (1 bit)


APB1CLKEN

APB1 clock enable register (RCM_APB1CLKEN)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1CLKEN APB1CLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR2CLKE TMR3CLKE TMR4CLKE TMR5CLKE TMR6CLKE TMR7CLKE WWDTCLKE SPI2CLKE SPI3CLKE USART2CLKE USART3CLKE UART4CLKE UART5CLKE I2C1CLKE I2C2CLKE USBCLKE CANCLKE BAKRCLKE PMUCLKE DACCLKE

TMR2CLKE : Timer 2 clock enable
bits : 0 - 0 (1 bit)

TMR3CLKE : Timer 3 clock enable
bits : 1 - 1 (1 bit)

TMR4CLKE : Timer 4 clock enable
bits : 2 - 2 (1 bit)

TMR5CLKE : Timer 5 clock enable
bits : 3 - 3 (1 bit)

TMR6CLKE : Timer 6 clock enable
bits : 4 - 4 (1 bit)

TMR7CLKE : Timer 7 clock enable
bits : 5 - 5 (1 bit)

WWDTCLKE : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2CLKE : SPI 2 clock enable
bits : 14 - 14 (1 bit)

SPI3CLKE : SPI 3 clock enable
bits : 15 - 15 (1 bit)

USART2CLKE : USART 2 clock enable
bits : 17 - 17 (1 bit)

USART3CLKE : USART 3 clock enable
bits : 18 - 18 (1 bit)

UART4CLKE : UART 4 clock enable
bits : 19 - 19 (1 bit)

UART5CLKE : UART 5 clock enable
bits : 20 - 20 (1 bit)

I2C1CLKE : I2C 1 clock enable
bits : 21 - 21 (1 bit)

I2C2CLKE : I2C 2 clock enable
bits : 22 - 22 (1 bit)

USBCLKE : USB clock enable
bits : 23 - 23 (1 bit)

CANCLKE : CAN clock enable
bits : 25 - 25 (1 bit)

BAKRCLKE : Bakr interface clock enable
bits : 27 - 27 (1 bit)

PMUCLKE : Power interface clock enable
bits : 28 - 28 (1 bit)

DACCLKE : DAC interface clock enable
bits : 29 - 29 (1 bit)


BD

Bakr domain control register (RCM_BD)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BD BD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXTEN LXTRDYF LXTBYP RTCSEL RTCEN BDRST

LXTEN : External Low Speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LXTRDYF : External Low Speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LXTBYP : External Low Speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Bakr domain software reset
bits : 16 - 16 (1 bit)
access : read-write


CSTS

Control/status register (RCM_CSTS)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSTS CSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIRCEN LIRCRDYF CLRRSTF PINRSTF PWRRSTF SWRSTF IWDTRSTF WWDTRSTF LPRRSTF

LIRCEN : Internal low speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LIRCRDYF : Internal low speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

CLRRSTF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PWRRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SWRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

IWDTRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDTRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


CFG

Clock configuration register (RCM_CFGR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCSEL SCS AHBDIV APB1DIV APB2DIV ADCDIV PLLSEL PLLXTDIV PLLMF USBDIV COC FPUDIV

SCSEL : System clock Switch
bits : 0 - 1 (2 bit)
access : read-write

SCS : System Clock Switch Status
bits : 2 - 3 (2 bit)
access : read-only

AHBDIV : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

APB1DIV : APB Low speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

APB2DIV : APB High speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

ADCDIV : ADC prescaler
bits : 14 - 15 (2 bit)
access : read-write

PLLSEL : PLL entry clock source
bits : 16 - 16 (1 bit)
access : read-write

PLLXTDIV : HSE divider for PLL entry
bits : 17 - 17 (1 bit)
access : read-write

PLLMF : PLL Multiplication Factor
bits : 18 - 21 (4 bit)
access : read-write

USBDIV : USB OTG FS prescaler
bits : 22 - 22 (1 bit)
access : read-write

COC : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write

FPUDIV :
bits : 27 - 27 (1 bit)
access : read-write


INT

Clock interrupt control register (RCM_INT)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIRCRDYIF LXTRDYIF HIRCRDYIF HXTRDYIF PLLRDYIF CSSIF LIRCRDYIE LXTRDYIE HIRCRDYIE HXTRDYIE PLLRDYIE LIRCRDYC LXTRDYC HIRCRDYC HXTRDYC PLLRDYC CSSIFC

LIRCRDYIF : LIR Ready Interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LXTRDYIF : LXT Ready Interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HIRCRDYIF : HIR Ready Interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HXTRDYIF : HXT Ready Interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYIF : PLL Ready Interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

CSSIF : Clock Security System Interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LIRCRDYIE : LIR Ready Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

LXTRDYIE : LXT Ready Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

HIRCRDYIE : HIR Ready Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HXTRDYIE : HXT Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : PLL Ready Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

LIRCRDYC : LIR Ready Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LXTRDYC : LXT Ready Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

HIRCRDYC : HIR Ready Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HXTRDYC : HXT Ready Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : PLL Ready Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

CSSIFC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only


APB2RST

APB2 peripheral reset register (RCM_APB2RST)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RST APB2RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIORST PARST PBRST PCRST PDRST PERST PFRST PGRST ADC1RST ADC2RST TMR1RST SPI1RST TMR8RST USART1RST ADC3RST

AFIORST : Alternate function I/O reset
bits : 0 - 0 (1 bit)

PARST : IO port A reset
bits : 2 - 2 (1 bit)

PBRST : IO port B reset
bits : 3 - 3 (1 bit)

PCRST : IO port C reset
bits : 4 - 4 (1 bit)

PDRST : IO port D reset
bits : 5 - 5 (1 bit)

PERST : IO port E reset
bits : 6 - 6 (1 bit)

PFRST : IO port F reset
bits : 7 - 7 (1 bit)

PGRST : IO port G reset
bits : 8 - 8 (1 bit)

ADC1RST : ADC 1 interface reset
bits : 9 - 9 (1 bit)

ADC2RST : ADC 2 interface reset
bits : 10 - 10 (1 bit)

TMR1RST : TMR1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

TMR8RST : TMR8 timer reset
bits : 13 - 13 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

ADC3RST : ADC 3 interface reset
bits : 15 - 15 (1 bit)



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