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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IF

PAC1

MAC1

SRC2

CNTTC2

PAC2

MAC2

SRC3

CNTTC3

PAC3

MAC3

IFR

SRC4

CNTTC4

PAC4

MAC4

SRC5

CNTTC5

PAC5

MAC5

SRC6

CNTTC6

PAC6

MAC6

SRC1

SRC7

CNTTC7

PAC7

MAC7

CNTTC1


IF

DMA Interrupt status register (DMA_IF)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIFC1 EOTTFC1 MOTIFC1 FOTIFC1 GIFC2 EOTTFC2 MOTIFC2 FOTIFC2 GIFC3 EOTTFC3 MOTIFC3 FOTIFC3 GIFC4 EOTTFC4 MOTIFC4 FOTIFC4 GIFC5 EOTTFC5 MOTIFC5 FOTIFC5 GIFC6 EOTTFC6 MOTIFC6 FOTIFC6 GIFC7 EOTTFC7 MOTIFC7 FOTIFC7

GIFC1 : Channel 1 Global interrupt flag
bits : 0 - 0 (1 bit)

EOTTFC1 : Channel 1 Transfer Complete flag
bits : 1 - 1 (1 bit)

MOTIFC1 : Channel 1 Half Transfer Complete flag
bits : 2 - 2 (1 bit)

FOTIFC1 : Channel 1 Transfer Error flag
bits : 3 - 3 (1 bit)

GIFC2 : Channel 2 Global interrupt flag
bits : 4 - 4 (1 bit)

EOTTFC2 : Channel 2 Transfer Complete flag
bits : 5 - 5 (1 bit)

MOTIFC2 : Channel 2 Half Transfer Complete flag
bits : 6 - 6 (1 bit)

FOTIFC2 : Channel 2 Transfer Error flag
bits : 7 - 7 (1 bit)

GIFC3 : Channel 3 Global interrupt flag
bits : 8 - 8 (1 bit)

EOTTFC3 : Channel 3 Transfer Complete flag
bits : 9 - 9 (1 bit)

MOTIFC3 : Channel 3 Half Transfer Complete flag
bits : 10 - 10 (1 bit)

FOTIFC3 : Channel 3 Transfer Error flag
bits : 11 - 11 (1 bit)

GIFC4 : Channel 4 Global interrupt flag
bits : 12 - 12 (1 bit)

EOTTFC4 : Channel 4 Transfer Complete flag
bits : 13 - 13 (1 bit)

MOTIFC4 : Channel 4 Half Transfer Complete flag
bits : 14 - 14 (1 bit)

FOTIFC4 : Channel 4 Transfer Error flag
bits : 15 - 15 (1 bit)

GIFC5 : Channel 5 Global interrupt flag
bits : 16 - 16 (1 bit)

EOTTFC5 : Channel 5 Transfer Complete flag
bits : 17 - 17 (1 bit)

MOTIFC5 : Channel 5 Half Transfer Complete flag
bits : 18 - 18 (1 bit)

FOTIFC5 : Channel 5 Transfer Error flag
bits : 19 - 19 (1 bit)

GIFC6 : Channel 6 Global interrupt flag
bits : 20 - 20 (1 bit)

EOTTFC6 : Channel 6 Transfer Complete flag
bits : 21 - 21 (1 bit)

MOTIFC6 : Channel 6 Half Transfer Complete flag
bits : 22 - 22 (1 bit)

FOTIFC6 : Channel 6 Transfer Error flag
bits : 23 - 23 (1 bit)

GIFC7 : Channel 7 Global interrupt flag
bits : 24 - 24 (1 bit)

EOTTFC7 : Channel 7 Transfer Complete flag
bits : 25 - 25 (1 bit)

MOTIFC7 : Channel 7 Half Transfer Complete flag
bits : 26 - 26 (1 bit)

FOTIFC7 : Channel 7 Transfer Error flag
bits : 27 - 27 (1 bit)


PAC1

DMA channel 1 peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC1 PAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC1

DMA channel 1 memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC1 MAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


SRC2

DMA channel 2 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC2 SRC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTTC2

DMA channel 2 number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC2 CNTTC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)


PAC2

DMA channel 2 peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC2 PAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC2

DMA channel 2 memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC2 MAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


SRC3

DMA channel 3 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC3 SRC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTTC3

DMA channel 3 number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC3 CNTTC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)


PAC3

DMA channel 3 peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC3 PAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC3

DMA channel 3 memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC3 MAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


IFR

DMA Interrupt reset register (DMA_IFR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFR IFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGIFC1 REOTIFC1 RMOTIFC1 RFOTIFC1 RGIFC2 REOTIFC2 RMOTIFC2 RFOTIFC2 RGIFC3 REOTIFC3 RMOTIFC3 RFOTIFC3 RGIFC4 REOTIFC4 RMOTIFC4 RFOTIFC4 RGIFC5 REOTIFC5 RMOTIFC5 RFOTIFC5 RGIFC6 REOTIFC6 RMOTIFC6 RFOTIFC6 RGIFC7 REOTIFC7 RMOTIFC7 RFOTIFC7

RGIFC1 : Channel 1 Global interrupt resetr
bits : 0 - 0 (1 bit)

REOTIFC1 : Channel 1 Transfer Complete reset
bits : 1 - 1 (1 bit)

RMOTIFC1 : Channel 1 Half Transfer reset
bits : 2 - 2 (1 bit)

RFOTIFC1 : Channel 1 Transfer Error reset
bits : 3 - 3 (1 bit)

RGIFC2 : Channel 2 Global interrupt reset
bits : 4 - 4 (1 bit)

REOTIFC2 : Channel 2 Transfer Complete reset
bits : 5 - 5 (1 bit)

RMOTIFC2 : Channel 2 Half Transfer reset
bits : 6 - 6 (1 bit)

RFOTIFC2 : Channel 2 Transfer Error reset
bits : 7 - 7 (1 bit)

RGIFC3 : Channel 3 Global interrupt reset
bits : 8 - 8 (1 bit)

REOTIFC3 : Channel 3 Transfer Complete reset
bits : 9 - 9 (1 bit)

RMOTIFC3 : Channel 3 Half Transfer reset
bits : 10 - 10 (1 bit)

RFOTIFC3 : Channel 3 Transfer Error reset
bits : 11 - 11 (1 bit)

RGIFC4 : Channel 4 Global interrupt reset
bits : 12 - 12 (1 bit)

REOTIFC4 : Channel 4 Transfer Complete reset
bits : 13 - 13 (1 bit)

RMOTIFC4 : Channel 4 Half Transfer reset
bits : 14 - 14 (1 bit)

RFOTIFC4 : Channel 4 Transfer Error reset
bits : 15 - 15 (1 bit)

RGIFC5 : Channel 5 Global interrupt reset
bits : 16 - 16 (1 bit)

REOTIFC5 : Channel 5 Transfer Complete reset
bits : 17 - 17 (1 bit)

RMOTIFC5 : Channel 5 Half Transfer reset
bits : 18 - 18 (1 bit)

RFOTIFC5 : Channel 5 Transfer Error reset
bits : 19 - 19 (1 bit)

RGIFC6 : Channel 6 Global interrupt reset
bits : 20 - 20 (1 bit)

REOTIFC6 : Channel 6 Transfer Complete reset
bits : 21 - 21 (1 bit)

RMOTIFC6 : Channel 6 Half Transfer reset
bits : 22 - 22 (1 bit)

RFOTIFC6 : Channel 6 Transfer Error reset
bits : 23 - 23 (1 bit)

RGIFC7 : Channel 7 Global interrupt reset
bits : 24 - 24 (1 bit)

REOTIFC7 : Channel 7 Transfer Complete reset
bits : 25 - 25 (1 bit)

RMOTIFC7 : Channel 7 Half Transfer reset
bits : 26 - 26 (1 bit)

RFOTIFC7 : Channel 7 Transfer Error reset
bits : 27 - 27 (1 bit)


SRC4

DMA channel 4 configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC4 SRC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTTC4

DMA channel 4 number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC4 CNTTC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)


PAC4

DMA channel 4 peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC4 PAC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC4

DMA channel 4 memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC4 MAC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


SRC5

DMA channel 5 configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC5 SRC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTTC5

DMA channel 5 number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC5 CNTTC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)


PAC5

DMA channel 5 peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC5 PAC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC5

DMA channel 5 memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC5 MAC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


SRC6

DMA channel 6 configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC6 SRC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTTC6

DMA channel 6 number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC6 CNTTC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)


PAC6

DMA channel 6 peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC6 PAC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC6

DMA channel 6 memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC6 MAC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


SRC1

DMA channel 1 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1 SRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


SRC7

DMA channel 7 configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC7 SRC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN EOTIEN MOTIEN FOTIEN DOT LOOP PLOOP MLOOP PWID MWID PL M2MEN

EN : Channel enable
bits : 0 - 0 (1 bit)

EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DOT : Data transfer direction
bits : 4 - 4 (1 bit)

LOOP : Circular mode
bits : 5 - 5 (1 bit)

PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)

MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)

PWID : Peripheral size
bits : 8 - 9 (2 bit)

MWID : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTTC7

DMA channel 7 number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC7 CNTTC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)


PAC7

DMA channel 7 peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAC7 PAC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC

PAC : Peripheral address
bits : 0 - 31 (32 bit)


MAC7

DMA channel 7 memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC7 MAC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC

MAC : Memory address
bits : 0 - 31 (32 bit)


CNTTC1

DMA channel 1 number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTC1 CNTTC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTTC

CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)



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