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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

STS

CTRL2

CTRL3

GTDIV

DATA

BR

CTRL1


STS

Status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEF FEF NEF OVREF IDLEF RXBNEF TXCF TXBEF LBDF CTSF

PEF : Parity error
bits : 0 - 0 (1 bit)
access : read-only

FEF : Framing error
bits : 1 - 1 (1 bit)
access : read-only

NEF : Noise error flag
bits : 2 - 2 (1 bit)
access : read-only

OVREF : Overrun error
bits : 3 - 3 (1 bit)
access : read-only

IDLEF : IDLE line detected
bits : 4 - 4 (1 bit)
access : read-only

RXBNEF : Read data register not empty
bits : 5 - 5 (1 bit)
access : read-write

TXCF : Transmission complete
bits : 6 - 6 (1 bit)
access : read-write

TXBEF : Transmit data register empty
bits : 7 - 7 (1 bit)
access : read-only

LBDF : LIN break detection flag
bits : 8 - 8 (1 bit)
access : read-write

CTSF : CTS flag
bits : 9 - 9 (1 bit)
access : read-write


CTRL2

Control register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR LBDL LBDIE LBCEN CLKPHA CLKPOL CKPEN STOPB LINEN

ADDR : Address of the USART node
bits : 0 - 3 (4 bit)

LBDL : lin break detection length
bits : 5 - 5 (1 bit)

LBDIE : LIN break detection interrupt enable
bits : 6 - 6 (1 bit)

LBCEN : Last bit clock pulse
bits : 8 - 8 (1 bit)

CLKPHA : Clock phase
bits : 9 - 9 (1 bit)

CLKPOL : Clock polarity
bits : 10 - 10 (1 bit)

CKPEN : Clock enable
bits : 11 - 11 (1 bit)

STOPB : STOP bits
bits : 12 - 13 (2 bit)

LINEN : LIN mode enable
bits : 14 - 14 (1 bit)


CTRL3

Control register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRIE IRDAEN IRDALP HDEN NACKEN SCEN RXDMAEN TXDMAEN RTSEN CTSEN CTSIE

ERRIE : Error interrupt enable
bits : 0 - 0 (1 bit)

IRDAEN : IrDA mode enable
bits : 1 - 1 (1 bit)

IRDALP : IrDA low-power
bits : 2 - 2 (1 bit)

HDEN : Half-duplex selection
bits : 3 - 3 (1 bit)

NACKEN : Smartcard NACK enable
bits : 4 - 4 (1 bit)

SCEN : Smartcard mode enable
bits : 5 - 5 (1 bit)

RXDMAEN : DMA enable receiver
bits : 6 - 6 (1 bit)

TXDMAEN : DMA enable transmitter
bits : 7 - 7 (1 bit)

RTSEN : RTS enable
bits : 8 - 8 (1 bit)

CTSEN : CTS enable
bits : 9 - 9 (1 bit)

CTSIE : CTS interrupt enable
bits : 10 - 10 (1 bit)


GTDIV

Guard time and divider number register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDIV GTDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV GT

DIV : Prescaler value
bits : 0 - 7 (8 bit)

GT : Guard time value
bits : 8 - 15 (8 bit)


DATA

TX Buffer Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data value
bits : 0 - 8 (9 bit)


BR

Baud rate register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACTION MANTISSA

FRACTION : fraction of USARTDIV
bits : 0 - 3 (4 bit)

MANTISSA : mantissa of USARTDIV
bits : 4 - 15 (12 bit)


CTRL1

Control register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBK RXWUP RXEN TXEN IDLEIE RXBNEIE TXCIE TXBEIE PEIE PMSEL PCEN WUPM WLS UEN

TXBK : Send break
bits : 0 - 0 (1 bit)

RXWUP : Receiver wakeup
bits : 1 - 1 (1 bit)

RXEN : Receiver enable
bits : 2 - 2 (1 bit)

TXEN : Transmitter enable
bits : 3 - 3 (1 bit)

IDLEIE : IDLE interrupt enable
bits : 4 - 4 (1 bit)

RXBNEIE : RXNE interrupt enable
bits : 5 - 5 (1 bit)

TXCIE : Transmission complete interrupt enable
bits : 6 - 6 (1 bit)

TXBEIE : TXE interrupt enable
bits : 7 - 7 (1 bit)

PEIE : PE interrupt enable
bits : 8 - 8 (1 bit)

PMSEL : Parity selection
bits : 9 - 9 (1 bit)

PCEN : Parity control enable
bits : 10 - 10 (1 bit)

WUPM : Wakeup method
bits : 11 - 11 (1 bit)

WLS : Word length
bits : 12 - 12 (1 bit)

UEN : USART enable
bits : 13 - 13 (1 bit)



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