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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

STS

SMPT2

IJOF1

IJOF2

IJOF3

IJOF4

AWDHT

AWDLT

RGSQ1

RGSQ2

RGSQ3

IJSQ

IJD1

CTRL1

IJD2

IJD3

IJD4

RDG

CTRL2

SMPT1


STS

status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDF CCF IJEOCF IJSTRF STRT

AWDF : Analog watchdog flag
bits : 0 - 0 (1 bit)

CCF : Regular channel end of conversion
bits : 1 - 1 (1 bit)

IJEOCF : Injected channel end of conversion
bits : 2 - 2 (1 bit)

IJSTRF : Injected channel start flag
bits : 3 - 3 (1 bit)

STRT : Regular channel start flag
bits : 4 - 4 (1 bit)


SMPT2

sample time register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPT2 SMPT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPT0 SMPT1 SMPT2 SMPT3 SMPT4 SMPT5 SMPT6 SMPT7 SMPT8 SMPT9

SMPT0 : Channel 0 sample time selection
bits : 0 - 2 (3 bit)

SMPT1 : Channel 1 sample time selection
bits : 3 - 5 (3 bit)

SMPT2 : Channel 2 sample time selection
bits : 6 - 8 (3 bit)

SMPT3 : Channel 3 sample time selection
bits : 9 - 11 (3 bit)

SMPT4 : Channel 4 sample time selection
bits : 12 - 14 (3 bit)

SMPT5 : Channel 5 sample time selection
bits : 15 - 17 (3 bit)

SMPT6 : Channel 6 sample time selection
bits : 18 - 20 (3 bit)

SMPT7 : Channel 7 sample time selection
bits : 21 - 23 (3 bit)

SMPT8 : Channel 8 sample time selection
bits : 24 - 26 (3 bit)

SMPT9 : Channel 9 sample time selection
bits : 27 - 29 (3 bit)


IJOF1

injected channel data offset register x
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IJOF1 IJOF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1

OFFSET1 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


IJOF2

injected channel data offset register x
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IJOF2 IJOF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET2

OFFSET2 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


IJOF3

injected channel data offset register x
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IJOF3 IJOF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET3

OFFSET3 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


IJOF4

injected channel data offset register x
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IJOF4 IJOF4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET4

OFFSET4 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


AWDHT

watchdog higher threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWDHT AWDHT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDHT

AWDHT : Analog watchdog higher threshold
bits : 0 - 11 (12 bit)


AWDLT

watchdog lower threshold register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWDLT AWDLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDLT

AWDLT : Analog watchdog lower threshold
bits : 0 - 11 (12 bit)


RGSQ1

regular sequence register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGSQ1 RGSQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGSQ13 RGSQ14 RGSQ15 RGSQ16 RGSL

RGSQ13 : 13th conversion in regular sequence
bits : 0 - 4 (5 bit)

RGSQ14 : 14th conversion in regular sequence
bits : 5 - 9 (5 bit)

RGSQ15 : 15th conversion in regular sequence
bits : 10 - 14 (5 bit)

RGSQ16 : 16th conversion in regular sequence
bits : 15 - 19 (5 bit)

RGSL : Regular channel sequence length
bits : 20 - 23 (4 bit)


RGSQ2

regular sequence register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGSQ2 RGSQ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGSQ7 RGSQ8 RGSQ9 RGSQ10 RGSQ11 RGSQ12

RGSQ7 : 7th conversion in regular sequence
bits : 0 - 4 (5 bit)

RGSQ8 : 8th conversion in regular sequence
bits : 5 - 9 (5 bit)

RGSQ9 : 9th conversion in regular sequence
bits : 10 - 14 (5 bit)

RGSQ10 : 10th conversion in regular sequence
bits : 15 - 19 (5 bit)

RGSQ11 : 11th conversion in regular sequence
bits : 20 - 24 (5 bit)

RGSQ12 : 12th conversion in regular sequence
bits : 25 - 29 (5 bit)


RGSQ3

regular sequence register 3
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGSQ3 RGSQ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGSQ1 RGSQ2 RGSQ3 RGSQ4 RGSQ5 RGSQ6

RGSQ1 : 1st conversion in regular sequence
bits : 0 - 4 (5 bit)

RGSQ2 : 2nd conversion in regular sequence
bits : 5 - 9 (5 bit)

RGSQ3 : 3rd conversion in regular sequence
bits : 10 - 14 (5 bit)

RGSQ4 : 4th conversion in regular sequence
bits : 15 - 19 (5 bit)

RGSQ5 : 5th conversion in regular sequence
bits : 20 - 24 (5 bit)

RGSQ6 : 6th conversion in regular sequence
bits : 25 - 29 (5 bit)


IJSQ

injected sequence register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IJSQ IJSQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IJSQ1 IJSQ2 IJSQ3 IJSQ4 IJSL

IJSQ1 : 1st conversion in injected sequence
bits : 0 - 4 (5 bit)

IJSQ2 : 2nd conversion in injected sequence
bits : 5 - 9 (5 bit)

IJSQ3 : 3rd conversion in injected sequence
bits : 10 - 14 (5 bit)

IJSQ4 : 4th conversion in injected sequence
bits : 15 - 19 (5 bit)

IJSL : Injected sequence length
bits : 20 - 21 (2 bit)


IJD1

injected data register x
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IJD1 IJD1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IJD

IJD : Injected data
bits : 0 - 15 (16 bit)


CTRL1

control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDCS EOCIEN AWDIEN IJEOCIEN SMEN AWDSC IJAEN RGDMEN IJDMEN DMCC DMS IJAWDEN RGAWDEN

AWDCS : Analog watchdog channel select bits
bits : 0 - 4 (5 bit)

EOCIEN : Interrupt enable for EOC
bits : 5 - 5 (1 bit)

AWDIEN : Analog watchdog interrupt enable
bits : 6 - 6 (1 bit)

IJEOCIEN : Interrupt enable for injected channels
bits : 7 - 7 (1 bit)

SMEN : Scan mode
bits : 8 - 8 (1 bit)

AWDSC : Enable the watchdog on a single channel in scan mode
bits : 9 - 9 (1 bit)

IJAEN : Automatic injected group conversion
bits : 10 - 10 (1 bit)

RGDMEN : Discontinuous mode on regular channels
bits : 11 - 11 (1 bit)

IJDMEN : Discontinuous mode on injected channels
bits : 12 - 12 (1 bit)

DMCC : Discontinuous mode channel count
bits : 13 - 15 (3 bit)

DMS : Dual mode selection
bits : 16 - 19 (4 bit)

IJAWDEN : Analog watchdog enable on injected channels
bits : 22 - 22 (1 bit)

RGAWDEN : Analog watchdog enable on regular channels
bits : 23 - 23 (1 bit)


IJD2

injected data register x
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IJD2 IJD2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IJD

IJD : Injected data
bits : 0 - 15 (16 bit)


IJD3

injected data register x
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IJD3 IJD3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IJD

IJD : Injected data
bits : 0 - 15 (16 bit)


IJD4

injected data register x
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IJD4 IJD4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IJD

IJD : Injected data
bits : 0 - 15 (16 bit)


RDG

regular data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDG RDG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA ADC2DATA

RDATA : Regular data
bits : 0 - 15 (16 bit)

ADC2DATA : ADC2 data
bits : 16 - 31 (16 bit)


CTRL2

control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCON CCM CALSTR CALRST DMAEN DAM IJEXTSEL IJEXTGEN RGEXTSEL RGEXTGEN IJSWSTR RGSWSTR TVEN

ADCON : A/D converter ON / OFF
bits : 0 - 0 (1 bit)

CCM : Continuous conversion
bits : 1 - 1 (1 bit)

CALSTR : A/D calibration
bits : 2 - 2 (1 bit)

CALRST : Reset calibration
bits : 3 - 3 (1 bit)

DMAEN : Direct memory access mode
bits : 8 - 8 (1 bit)

DAM : Data alignment
bits : 11 - 11 (1 bit)

IJEXTSEL : External event select for injected group
bits : 12 - 14 (3 bit)

IJEXTGEN : External trigger conversion mode for injected channels
bits : 15 - 15 (1 bit)

RGEXTSEL : External event select for regular group
bits : 17 - 19 (3 bit)

RGEXTGEN : External trigger conversion mode for regular channels
bits : 20 - 20 (1 bit)

IJSWSTR : Start conversion of injected channels
bits : 21 - 21 (1 bit)

RGSWSTR : Start conversion of regular channels
bits : 22 - 22 (1 bit)

TVEN : Temperature sensor and VREFINT enable
bits : 23 - 23 (1 bit)


SMPT1

sample time register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPT1 SMPT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPT10 SMPT11 SMPT12 SMPT13 SMPT14 SMPT15 SMPT16 SMPT17

SMPT10 : Channel 10 sample time selection
bits : 0 - 2 (3 bit)

SMPT11 : Channel 11 sample time selection
bits : 3 - 5 (3 bit)

SMPT12 : Channel 12 sample time selection
bits : 6 - 8 (3 bit)

SMPT13 : Channel 13 sample time selection
bits : 9 - 11 (3 bit)

SMPT14 : Channel 14 sample time selection
bits : 12 - 14 (3 bit)

SMPT15 : Channel 15 sample time selection
bits : 15 - 17 (3 bit)

SMPT16 : Channel 16 sample time selection
bits : 18 - 20 (3 bit)

SMPT17 : Channel 17 sample time selection
bits : 21 - 23 (3 bit)



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