\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Power control register (PMU_CTRL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPSM : Low Power Deep Sleep
bits : 0 - 0 (1 bit)
SBMDS : Power Down Deep Sleep
bits : 1 - 1 (1 bit)
RWUPF : Clear Wake-up Flag
bits : 2 - 2 (1 bit)
RSBF : Clear STANDBY Flag
bits : 3 - 3 (1 bit)
PVMEN : Power Voltage Detector Enable
bits : 4 - 4 (1 bit)
PLMS : PVD Level Selection
bits : 5 - 7 (3 bit)
BAKRWEN : Disable Bakr Domain write protection
bits : 8 - 8 (1 bit)
Power control/status register (PMU_CTRLF)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUPF : Wake-Up Flag
bits : 0 - 0 (1 bit)
access : read-only
SBMF : STANDBY Flag
bits : 1 - 1 (1 bit)
access : read-only
PVMF : PVD Output
bits : 2 - 2 (1 bit)
access : read-only
WUPEN : Enable WKUP pin
bits : 8 - 8 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.