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PMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

CTRLF


CTRL

Power control register (PMU_CTRL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSM SBMDS RWUPF RSBF PVMEN PLMS BAKRWEN

LPSM : Low Power Deep Sleep
bits : 0 - 0 (1 bit)

SBMDS : Power Down Deep Sleep
bits : 1 - 1 (1 bit)

RWUPF : Clear Wake-up Flag
bits : 2 - 2 (1 bit)

RSBF : Clear STANDBY Flag
bits : 3 - 3 (1 bit)

PVMEN : Power Voltage Detector Enable
bits : 4 - 4 (1 bit)

PLMS : PVD Level Selection
bits : 5 - 7 (3 bit)

BAKRWEN : Disable Bakr Domain write protection
bits : 8 - 8 (1 bit)


CTRLF

Power control/status register (PMU_CTRLF)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLF CTRLF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUPF SBMF PVMF WUPEN

WUPF : Wake-Up Flag
bits : 0 - 0 (1 bit)
access : read-only

SBMF : STANDBY Flag
bits : 1 - 1 (1 bit)
access : read-only

PVMF : PVD Output
bits : 2 - 2 (1 bit)
access : read-only

WUPEN : Enable WKUP pin
bits : 8 - 8 (1 bit)
access : read-write



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