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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL1

DATA

SWITCH

STS1

STS2

CLKCTRL

TRISE

CTRL2

ADD1

ADD2


CTRL1

Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2CEN SMB SMBT ARPEN PECEN BCEN STRDIS STA STOP ACKEN ACKPOS TPECEN SMB_ALT SWRST

I2CEN : Peripheral enable
bits : 0 - 0 (1 bit)

SMB : SMBus mode
bits : 1 - 1 (1 bit)

SMBT : SMBus type
bits : 3 - 3 (1 bit)

ARPEN : ARP enable
bits : 4 - 4 (1 bit)

PECEN : PEC enable
bits : 5 - 5 (1 bit)

BCEN : General call enable
bits : 6 - 6 (1 bit)

STRDIS : Clock stretching disable (Slave mode)
bits : 7 - 7 (1 bit)

STA : Start generation
bits : 8 - 8 (1 bit)

STOP : Stop generation
bits : 9 - 9 (1 bit)

ACKEN : Acknowledge enable
bits : 10 - 10 (1 bit)

ACKPOS : Acknowledge/PEC Position (for data reception)
bits : 11 - 11 (1 bit)

TPECEN : Packet error checking
bits : 12 - 12 (1 bit)

SMB_ALT : SMBus alert
bits : 13 - 13 (1 bit)

SWRST : Software reset
bits : 15 - 15 (1 bit)


DATA

Data register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : 8-bit data register
bits : 0 - 7 (8 bit)


SWITCH

I2C Switching register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWITCH SWITCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH

SWITCH : I2C Switching
bits : 0 - 0 (1 bit)


STS1

Status register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS1 STS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBTCF ADDRF BTCF ADDR10F SBDF RXBENF TXBENF BEF ALF AEF OUF PECEF TIMEOUT SMB_ALTF

SBTCF : Start bit (Master mode)
bits : 0 - 0 (1 bit)
access : read-only

ADDRF : Address sent (master mode)/matched (slave mode)
bits : 1 - 1 (1 bit)
access : read-only

BTCF : Byte transfer finished
bits : 2 - 2 (1 bit)
access : read-only

ADDR10F : 10-bit header sent (Master mode)
bits : 3 - 3 (1 bit)
access : read-only

SBDF : Stop detection (slave mode)
bits : 4 - 4 (1 bit)
access : read-only

RXBENF : Data register not empty (receivers)
bits : 6 - 6 (1 bit)
access : read-only

TXBENF : Data register empty (transmitters)
bits : 7 - 7 (1 bit)
access : read-only

BEF : Bus error
bits : 8 - 8 (1 bit)
access : read-write

ALF : Arbitration lost (master mode)
bits : 9 - 9 (1 bit)
access : read-write

AEF : Acknowledge failure
bits : 10 - 10 (1 bit)
access : read-write

OUF : Overrun/Underrun
bits : 11 - 11 (1 bit)
access : read-write

PECEF : PEC Error in reception
bits : 12 - 12 (1 bit)
access : read-write

TIMEOUT : Timeout or Tlow error
bits : 14 - 14 (1 bit)
access : read-write

SMB_ALTF : SMBus alert
bits : 15 - 15 (1 bit)
access : read-write


STS2

Status register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STS2 STS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMF BUSYF RWMF RBF SMB_DAF SMB_HHF DMAF PEC_DATA

MMF : Master/slave
bits : 0 - 0 (1 bit)

BUSYF : Bus busy
bits : 1 - 1 (1 bit)

RWMF : Transmitter/receiver
bits : 2 - 2 (1 bit)

RBF : General call address (Slave mode)
bits : 4 - 4 (1 bit)

SMB_DAF : SMBus device default address (Slave mode)
bits : 5 - 5 (1 bit)

SMB_HHF : SMBus host header (Slave mode)
bits : 6 - 6 (1 bit)

DMAF : Dual flag (Slave mode)
bits : 7 - 7 (1 bit)

PEC_DATA : acket error checking register
bits : 8 - 15 (8 bit)


CLKCTRL

Clock control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDR FMDC FASTMODE

CDR : Clock control register in Fast/Standard mode (Master mode)
bits : 0 - 11 (12 bit)

FMDC : Fast mode duty cycle
bits : 14 - 14 (1 bit)

FASTMODE : I2C master mode selection
bits : 15 - 15 (1 bit)


TRISE

TRISE register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRISE TRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRISE

TRISE : Maximum rise time in Fast/Standard mode (Master mode)
bits : 0 - 5 (6 bit)


CTRL2

Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ ERRIE EVTIE BUFIE DMAEN LAST

FREQ : Peripheral clock frequency
bits : 0 - 5 (6 bit)

ERRIE : Error interrupt enable
bits : 8 - 8 (1 bit)

EVTIE : Event interrupt enable
bits : 9 - 9 (1 bit)

BUFIE : Buffer interrupt enable
bits : 10 - 10 (1 bit)

DMAEN : DMA requests enable
bits : 11 - 11 (1 bit)

LAST : DMA last transfer
bits : 12 - 12 (1 bit)


ADD1

Own address register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADD1 ADD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD0 ADD1_7 ADD8_9 ADDCFG ADDMODE

ADD0 : Interface address
bits : 0 - 0 (1 bit)

ADD1_7 : Interface address
bits : 1 - 7 (7 bit)

ADD8_9 : Interface address
bits : 8 - 9 (2 bit)

ADDCFG :
bits : 15 - 15 (1 bit)

ADDMODE : Addressing mode (slave mode)
bits : 16 - 16 (1 bit)


ADD2

Own address register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADD2 ADD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUALEN ADD2

DUALEN : Dual addressing mode enable
bits : 0 - 0 (1 bit)

ADD2 : Interface address
bits : 1 - 7 (7 bit)



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