\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Key register (IWDT_KEYWORD)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYWORD : Key value
bits : 0 - 15 (16 bit)
Frequency Divider register (IWDT_DIV)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Prescaler divider
bits : 0 - 2 (3 bit)
Reload values register (IWDT_CNTRLD)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTRLD : Watchdog counter reload value
bits : 0 - 11 (12 bit)
Status register (IWDT_STS)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DVU : Watchdog prescaler value update
bits : 0 - 0 (1 bit)
CNTRU : Watchdog counter reload value update
bits : 1 - 1 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.