\n

SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR1 (CTRL1)

CRCPR (CRCPOLY)

RXCRCR (RXCRC)

TXCRCR (TXCRC)

CR2 (CTRL2)

SR (STS)

DR (DATA)


CR1 (CTRL1)

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPHA CLKPOL MSTMODE BRC SPIEN LSBF ISS SSC UMRXO DFL CRCNXT CRCEN BMTX BMEN

CLKPHA :
bits : 0 - 0 (1 bit)

CLKPOL :
bits : 1 - 1 (1 bit)

MSTMODE :
bits : 2 - 2 (1 bit)

BRC :
bits : 3 - 5 (3 bit)

SPIEN : SPI enable
bits : 6 - 6 (1 bit)

LSBF :
bits : 7 - 7 (1 bit)

ISS : Internal slave select
bits : 8 - 8 (1 bit)

SSC :
bits : 9 - 9 (1 bit)

UMRXO : Receive only
bits : 10 - 10 (1 bit)

DFL : Data frame format
bits : 11 - 11 (1 bit)

CRCNXT : CRC transfer next
bits : 12 - 12 (1 bit)

CRCEN : Hardware CRC calculation enable
bits : 13 - 13 (1 bit)

BMTX : Output enable in bidirectional mode
bits : 14 - 14 (1 bit)

BMEN : Bidirectional data mode enable
bits : 15 - 15 (1 bit)


CRCPR (CRCPOLY)

CRC polynomial register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCPR CRCPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCPOLY

CRCPOLY : CRC polynomial register
bits : 0 - 15 (16 bit)


RXCRCR (RXCRC)

RX CRC register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXCRCR RXCRCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRC

RXCRC : Rx CRC register
bits : 0 - 15 (16 bit)


TXCRCR (TXCRC)

TX CRC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXCRCR TXCRCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCRC

TXCRC : Tx CRC register
bits : 0 - 15 (16 bit)


CR2 (CTRL2)

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_DMAEN TX_DMAEN SSOEN ERRIE RXBNEIE TXBEIE

RX_DMAEN : Rx buffer DMA enable
bits : 0 - 0 (1 bit)

TX_DMAEN : Tx buffer DMA enable
bits : 1 - 1 (1 bit)

SSOEN : SS output enable
bits : 2 - 2 (1 bit)

ERRIE : Error interrupt enable
bits : 5 - 5 (1 bit)

RXBNEIE : RX buffer not empty interrupt enable
bits : 6 - 6 (1 bit)

TXBEIE : Tx buffer empty interrupt enable
bits : 7 - 7 (1 bit)


SR (STS)

status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBNEF TXBEF ST UDF CRCEF MEF RXOF BUSYF

RXBNEF : Receive buffer not empty
bits : 0 - 0 (1 bit)
access : read-only

TXBEF : Transmit buffer empty
bits : 1 - 1 (1 bit)
access : read-only

ST : Channel side
bits : 2 - 2 (1 bit)
access : read-only

UDF : Underrun flag
bits : 3 - 3 (1 bit)
access : read-only

CRCEF : CRC error flag
bits : 4 - 4 (1 bit)
access : read-write

MEF : Mode fault
bits : 5 - 5 (1 bit)
access : read-only

RXOF : Overrun flag
bits : 6 - 6 (1 bit)
access : read-only

BUSYF : Busy flag
bits : 7 - 7 (1 bit)
access : read-only


DR (DATA)

data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data register
bits : 0 - 15 (16 bit)



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