\n

NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1001 byte (0x0)
mem_usage : registers
protection :

Registers

ISER0

ISER1

ICER0

ICER1

ISPR0

ISPR1

ICPR0

ICPR1

IABR0

IABR1

ICTR

IPR0

IPR1

IPR2

IPR3

IPR4

IPR5

IPR6

IPR7

IPR8

IPR9

IPR10

IPR11

IPR12

IPR13

IPR14

STIR


ISER0

Interrupt Set-Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER0 ISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : SETENA
bits : 0 - 31 (32 bit)


ISER1

Interrupt Set-Enable Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER1 ISER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : SETENA
bits : 0 - 31 (32 bit)


ICER0

Interrupt Clear-Enable Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER0 ICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : CLRENA
bits : 0 - 31 (32 bit)


ICER1

Interrupt Clear-Enable Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER1 ICER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : CLRENA
bits : 0 - 31 (32 bit)


ISPR0

Interrupt Set-Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR0 ISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : SETPEND
bits : 0 - 31 (32 bit)


ISPR1

Interrupt Set-Pending Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR1 ISPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : SETPEND
bits : 0 - 31 (32 bit)


ICPR0

Interrupt Clear-Pending Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR0 ICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)


ICPR1

Interrupt Clear-Pending Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR1 ICPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)


IABR0

Interrupt Active Bit Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IABR0 IABR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)


IABR1

Interrupt Active Bit Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IABR1 IABR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)


ICTR

Interrupt Controller Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICTR ICTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTLINESNUM

INTLINESNUM : Total number of interrupt lines in groups
bits : 0 - 3 (4 bit)


IPR0

Interrupt Priority Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR0 IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR1

Interrupt Priority Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR2

Interrupt Priority Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR3

Interrupt Priority Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR3 IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR4

Interrupt Priority Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR4 IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR5

Interrupt Priority Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR5 IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR6

Interrupt Priority Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR6 IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR7

Interrupt Priority Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR7 IPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR8

Interrupt Priority Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR8 IPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR9

Interrupt Priority Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR9 IPR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR10

Interrupt Priority Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR10 IPR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR11

Interrupt Priority Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR11 IPR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR12

Interrupt Priority Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR12 IPR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR13

Interrupt Priority Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR13 IPR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR14

Interrupt Priority Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR14 IPR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


STIR

Software Triggered Interrupt Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

STIR STIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : interrupt to be triggered
bits : 0 - 8 (9 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.