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TM41

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

TCR10

TMR10

TMR11

TMR12

TMR13

TDR10

TDR11

TDR11L

TDR11H

TDR12

TDR13

TDR13L

TDR13H

TCR11

TSR10

TSR11

TSR12

TSR13

TE1

TS1

TT1

TPS1

TO1

TOE1

TOL1

TOM1

TCR12

TCR13


TCR10

Timer count register 0%s
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR10 TCR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMR10

Timer mode register mn
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR10 TMR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD CIS STS CCS CKS

MD : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

CCS : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TMR11

Timer mode register mn
address_offset : 0x12 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR11 TMR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD CIS STS SPLIT CCS CKS

MD : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

SPLIT : Selection of 8 or 16-bit timer operation for channels 1 and 3
bits : 11 - 22 (12 bit)
access : read-write

CCS : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TMR12

Timer mode register mn
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR12 TMR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD CIS STS MASTER CCS CKS

MD : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

MASTER : Selection between using channel n independently or simultaneously with another channel (as a slave or master)
bits : 11 - 22 (12 bit)
access : read-write

CCS : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TMR13

Timer mode register mn
address_offset : 0x16 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR13 TMR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD CIS STS SPLIT CCS CKS

MD : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

SPLIT : Selection of 8 or 16-bit timer operation for channels 1 and 3
bits : 11 - 22 (12 bit)
access : read-write

CCS : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TDR10

Timer data register 0%s
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR10 TDR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR11

Timer data register 0%s
address_offset : 0x19A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR11 TDR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR11L

Timer data lower register 01
address_offset : 0x19A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR11
reset_Mask : 0x0

TDR11L TDR11L read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR11H

Timer data higher register 01
address_offset : 0x19B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR11
reset_Mask : 0x0

TDR11H TDR11H read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR12

Timer data register 0%s
address_offset : 0x1E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR12 TDR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR13

Timer data register 0%s
address_offset : 0x1E6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR13 TDR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR13L

Timer data lower register 03
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR13
reset_Mask : 0x0

TDR13L TDR13L read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR13H

Timer data higher register 03
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR13
reset_Mask : 0x0

TDR13H TDR13H read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TCR11

Timer count register 0%s
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR11 TCR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR10

Timer status register mn
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSR10 TSR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF

OVF : Counter overflow status of channel n
bits : 0 - 0 (1 bit)


TSR11

Timer status register mn
address_offset : 0x22 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR11 TSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR12

Timer status register mn
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR12 TSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR13

Timer status register mn
address_offset : 0x26 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR13 TSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TE1

Timer channel enable status register m
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TE1 TE1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TE10 TE11 TE12 TE13 TEH11 TEH13

TE10 : Indication of operation enable/stop status of channel 0
bits : 0 - 0 (1 bit)

TE11 : Indication of operation enable/stop status of channel 1
bits : 1 - 2 (2 bit)

TE12 : Indication of operation enable/stop status of channel 2
bits : 2 - 4 (3 bit)

TE13 : Indication of operation enable/stop status of channel 3
bits : 3 - 6 (4 bit)

TEH11 : Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode
bits : 9 - 18 (10 bit)

TEH13 : Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode
bits : 11 - 22 (12 bit)


TS1

Timer channel start register 0
address_offset : 0x32 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TS1 TS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS10 TS11 TS12 TS13 TSH11 TSH13

TS10 : Operation enable (start) trigger of channel 0
bits : 0 - 0 (1 bit)

TS11 : Operation enable (start) trigger of channel 1
bits : 1 - 2 (2 bit)

TS12 : Operation enable (start) trigger of channel 2
bits : 2 - 4 (3 bit)

TS13 : Operation enable (start) trigger of channel 3
bits : 3 - 6 (4 bit)

TSH11 : Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
bits : 9 - 18 (10 bit)

TSH13 : Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
bits : 11 - 22 (12 bit)


TT1

Timer channel stop register 0
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TT1 TT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TT10 TT11 TT12 TT13 TTH11 TTH13

TT10 : Operation stop trigger of channel 0
bits : 0 - 0 (1 bit)

TT11 : Operation stop trigger of channel 1
bits : 1 - 2 (2 bit)

TT12 : Operation stop trigger of channel 2
bits : 2 - 4 (3 bit)

TT13 : Operation stop trigger of channel 3
bits : 3 - 6 (4 bit)

TTH11 : Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
bits : 9 - 18 (10 bit)

TTH13 : Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
bits : 11 - 22 (12 bit)


TPS1

Timer clock select register 0
address_offset : 0x36 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPS1 TPS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS10 PRS11 PRS12 PRS13

PRS10 : Prescaler 0
bits : 0 - 3 (4 bit)

PRS11 : Prescaler 1
bits : 4 - 11 (8 bit)

PRS12 : Prescaler 2
bits : 8 - 17 (10 bit)

PRS13 : Prescaler 3
bits : 12 - 25 (14 bit)


TO1

Timer output register 0
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TO1 TO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO10 TO11 TO12 TO13

TO10 : Timer output of channel 0
bits : 0 - 0 (1 bit)

TO11 : Timer output of channel 1
bits : 1 - 2 (2 bit)

TO12 : Timer output of channel 2
bits : 2 - 4 (3 bit)

TO13 : Timer output of channel 3
bits : 3 - 6 (4 bit)


TOE1

Timer output enable register 0
address_offset : 0x3A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOE1 TOE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOE10 TOE11 TOE12 TOE13

TOE10 : Timer output enable of channel 0
bits : 0 - 0 (1 bit)

TOE11 : Timer output enable of channel 1
bits : 1 - 2 (2 bit)

TOE12 : Timer output enable of channel 2
bits : 2 - 4 (3 bit)

TOE13 : Timer output enable of channel 3
bits : 3 - 6 (4 bit)


TOL1

Timer output level register 0
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOL1 TOL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOL11 TOL12 TOL13

TOL11 : Control of timer output level of channel 1
bits : 1 - 2 (2 bit)

TOL12 : Control of timer output level of channel 2
bits : 2 - 4 (3 bit)

TOL13 : Control of timer output level of channel 3
bits : 3 - 6 (4 bit)


TOM1

Timer output mode register 0
address_offset : 0x3E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOM1 TOM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOM11 TOM12 TOM13

TOM11 : Control of timer output mode of channel 1
bits : 1 - 2 (2 bit)

TOM12 : Control of timer output mode of channel 2
bits : 2 - 4 (3 bit)

TOM13 : Control of timer output mode of channel 3
bits : 3 - 6 (4 bit)


TCR12

Timer count register 0%s
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR12 TCR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCR13

Timer count register 0%s
address_offset : 0x6 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR13 TCR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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