\n

CMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

COMPMDR

COMPFIR

COMPOCR

CVRCTL

C0RVM

C1RVM

CMPSEL0

CMPSEL1


COMPMDR

Comparator mode setting register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPMDR COMPMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0ENB C0MON C1ENB C1MON

C0ENB : Comparator 0 operation 1enable
bits : 0 - 0 (1 bit)

C0MON : Comparator 0 monitor flag
bits : 3 - 6 (4 bit)

C1ENB : Comparator 1 operation enable
bits : 4 - 8 (5 bit)

C1MON : Comparator 1 monitor flag
bits : 7 - 14 (8 bit)


COMPFIR

Comparator filter control register
address_offset : 0x1 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPFIR COMPFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0FCK C0EPO C0EDG C1FCK C1EPO C1EDG

C0FCK : Comparator 0 filter selection
bits : 0 - 1 (2 bit)

C0EPO : Comparator 0 edge polarity switching
bits : 2 - 4 (3 bit)

C0EDG : Comparator 0 edge detection selection
bits : 3 - 6 (4 bit)

C1FCK : Comparator 1 filter selection
bits : 4 - 9 (6 bit)

C1EPO : Comparator 1 edge polarity switching
bits : 6 - 12 (7 bit)

C1EDG : Comparator 1 edge detection selection
bits : 7 - 14 (8 bit)


COMPOCR

Comparator output control register
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPOCR COMPOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0IE C0OE C0OP C1IE C1OE C1OP C1OTWMD

C0IE : Comparator 0 interrupt request enable
bits : 0 - 0 (1 bit)

C0OE : VOUT0 pin output enable
bits : 1 - 2 (2 bit)

C0OP : VOUT0 output polarity selection
bits : 2 - 4 (3 bit)

C1IE : Comparator 1 interrupt request enable
bits : 4 - 8 (5 bit)

C1OE : VOUT1 pin output enable
bits : 5 - 10 (6 bit)

C1OP : VOUT1 output polarity selection
bits : 6 - 12 (7 bit)

C1OTWMD : TIMER WINDOW output mode control bit of comparator 1
bits : 7 - 14 (8 bit)


CVRCTL

Comparator internal reference voltage control register
address_offset : 0x3 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CVRCTL CVRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVRVS0 CVRE0 CVRVS1 CVRE1

CVRVS0 : Power supply selection bit for internal reference voltage
bits : 0 - 0 (1 bit)

CVRE0 : Control bit for internal reference voltage 0
bits : 1 - 2 (2 bit)

CVRVS1 : Ground selection bit for internal reference voltage
bits : 4 - 8 (5 bit)

CVRE1 : Control bit for internal reference voltage 1
bits : 5 - 10 (6 bit)


C0RVM

Comparator internal reference voltage select register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0RVM C0RVM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

C1RVM

Comparator internal reference voltage select register 1
address_offset : 0x5 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1RVM C1RVM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CMPSEL0

Comparator 0 input signal selection control register
address_offset : 0xA Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPSEL0 CMPSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0REFS CMP0SEL

C0REFS : Selection of the input signal on the negative side of Comparator 0
bits : 0 - 1 (2 bit)

CMP0SEL : Selection of the input signal on the positive side of Comparator 0
bits : 7 - 14 (8 bit)


CMPSEL1

Comparator 1 input signal selection control register
address_offset : 0xB Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPSEL1 CMPSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C1REFS CMP1SEL

C1REFS : Selection of the input signal on the negative side of Comparator 1
bits : 0 - 2 (3 bit)

CMP1SEL : Selection of the input signal on the positive side of Comparator 1
bits : 6 - 13 (8 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.