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PORT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

P0

P1

PSET0

PSET1

PSET2

PSET3

PSET4

PSET5

PSET6

PSET7

PSET12

PSET13

PSET14

P2

PM0

PM1

PM2

PM3

PM4

PM5

PM6

PM7

PM12

PM13

PM14

P3

PU0

PU1

PU2

PU3

PU4

PU5

PU6

PU7

PU12

PU13

PU14

P4

PD0

PD1

PD2

PD3

PD5

PD6

PD7

PD12

PD13

PD14

P5

POM0

POM1

POM2

POM3

POM4

POM5

POM6

POM7

POM12

POM13

POM14

P6

PMC0

PMC1

PMC2

PMC3

PMC5

PMC6

PMC7

PMC12

PMC13

PMC14

P7

PCLR0

PCLR1

PCLR2

PCLR3

PCLR4

PCLR5

PCLR6

PCLR7

PCLR12

PCLR13

PCLR14

P00CFG

P01CFG

P10CFG

P11CFG

P12CFG

P13CFG

P14CFG

P15CFG

P16CFG

P17CFG

P20CFG

P21CFG

P22CFG

P23CFG

P24CFG

P25CFG

P26CFG

P27CFG

P30CFG

P31CFG

P40CFG

P41CFG

P50CFG

P51CFG

P60CFG

P61CFG

P62CFG

P63CFG

P70CFG

P71CFG

P72CFG

P73CFG

P74CFG

P75CFG

P120CFG

P121CFG

P122CFG

P123CFG

P124CFG

P130CFG

P136CFG

P137CFG

P140CFG

P146CFG

P147CFG

TI10PCFG

TI11PCFG

TI12PCFG

TI13PCFG

INTP0PCFG

INTP1PCFG

INTP2PCFG

INTP3PCFG

SDI00PCFG

SDA00PCFG

RXD0PCFG

SCLKI00PCFG

SS00PCFG

SDI20PCFG

IRRXDPCFG

RXD2PCFG

SCLKI20PCFG

SDAA0PCFG

SCLA0PCFG

RXD1PCFG

SDA10PCFG

SDI10PCFG

PMS

SPIPCFG

P12

P13

P14


P0

Port register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0 P0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P00 P01

P00 : P0%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P01 : P0%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write


P1

Port register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1 P1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P10 P11 P12 P13 P14 P15 P16 P17

P10 : P1%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P11 : P1%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write

P12 : P1%s input/output data register
bits : 2 - 2 (1 bit)
access : read-write

P13 : P1%s input/output data register
bits : 3 - 3 (1 bit)
access : read-write

P14 : P1%s input/output data register
bits : 4 - 4 (1 bit)
access : read-write

P15 : P1%s input/output data register
bits : 5 - 5 (1 bit)
access : read-write

P16 : P1%s input/output data register
bits : 6 - 6 (1 bit)
access : read-write

P17 : P1%s input/output data register
bits : 7 - 7 (1 bit)
access : read-write


PSET0

Port set register 0
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET0 PSET0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET1

Port set register 1
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET1 PSET1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET2

Port set register 2
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET2 PSET2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET3

Port set register 3
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET3 PSET3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET4

Port set register 4
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET4 PSET4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET5

Port set register 5
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET5 PSET5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET6

Port set register 6
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET6 PSET6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET7

Port set register 7
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET7 PSET7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET12

Port set register 12
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET12 PSET12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET13

Port set register 13
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET13 PSET13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PSET14

Port set register 14
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSET14 PSET14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

P2

Port register 2
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2 P2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P20 P21 P22 P23 P24 P25 P26 P27

P20 : P2%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P21 : P2%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write

P22 : P2%s input/output data register
bits : 2 - 2 (1 bit)
access : read-write

P23 : P2%s input/output data register
bits : 3 - 3 (1 bit)
access : read-write

P24 : P2%s input/output data register
bits : 4 - 4 (1 bit)
access : read-write

P25 : P2%s input/output data register
bits : 5 - 5 (1 bit)
access : read-write

P26 : P2%s input/output data register
bits : 6 - 6 (1 bit)
access : read-write

P27 : P2%s input/output data register
bits : 7 - 7 (1 bit)
access : read-write


PM0

Port mode register 0
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM0 PM0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM00 PM01

PM00 : P0%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM01 : P0%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write


PM1

Port mode register 1
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM1 PM1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM10 PM11 PM12 PM13 PM14 PM15 PM16 PM17

PM10 : P1%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM11 : P1%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write

PM12 : P1%s I/O mode select
bits : 2 - 2 (1 bit)
access : read-write

PM13 : P1%s I/O mode select
bits : 3 - 3 (1 bit)
access : read-write

PM14 : P1%s I/O mode select
bits : 4 - 4 (1 bit)
access : read-write

PM15 : P1%s I/O mode select
bits : 5 - 5 (1 bit)
access : read-write

PM16 : P1%s I/O mode select
bits : 6 - 6 (1 bit)
access : read-write

PM17 : P1%s I/O mode select
bits : 7 - 7 (1 bit)
access : read-write


PM2

Port mode register 2
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM2 PM2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM20 PM21 PM22 PM23 PM24 PM25 PM26 PM27

PM20 : P2%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM21 : P2%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write

PM22 : P2%s I/O mode select
bits : 2 - 2 (1 bit)
access : read-write

PM23 : P2%s I/O mode select
bits : 3 - 3 (1 bit)
access : read-write

PM24 : P2%s I/O mode select
bits : 4 - 4 (1 bit)
access : read-write

PM25 : P2%s I/O mode select
bits : 5 - 5 (1 bit)
access : read-write

PM26 : P2%s I/O mode select
bits : 6 - 6 (1 bit)
access : read-write

PM27 : P2%s I/O mode select
bits : 7 - 7 (1 bit)
access : read-write


PM3

Port mode register 3
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM3 PM3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM30 PM31

PM30 : P3%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM31 : P3%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write


PM4

Port mode register 4
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM4 PM4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM40 PM41

PM40 : P4%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM41 : P4%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write


PM5

Port mode register 5
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM5 PM5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM50 PM51

PM50 : P5%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM51 : P5%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write


PM6

Port mode register 6
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM6 PM6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM60 PM61 PM62 PM63

PM60 : P6%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM61 : P6%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write

PM62 : P6%s I/O mode select
bits : 2 - 2 (1 bit)
access : read-write

PM63 : P6%s I/O mode select
bits : 3 - 3 (1 bit)
access : read-write


PM7

Port mode register 7
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM7 PM7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM70 PM71 PM72 PM73 PM74 PM75

PM70 : P7%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM71 : P7%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write

PM72 : P7%s I/O mode select
bits : 2 - 2 (1 bit)
access : read-write

PM73 : P7%s I/O mode select
bits : 3 - 3 (1 bit)
access : read-write

PM74 : P7%s I/O mode select
bits : 4 - 4 (1 bit)
access : read-write

PM75 : P7%s I/O mode select
bits : 5 - 5 (1 bit)
access : read-write


PM12

Port mode register 12
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM12 PM12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM120 PM121 PM122 PM123 PM124

PM120 : P12%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM121 : P12%s I/O mode select
bits : 1 - 1 (1 bit)
access : read-write

PM122 : P12%s I/O mode select
bits : 2 - 2 (1 bit)
access : read-write

PM123 : P12%s I/O mode select
bits : 3 - 3 (1 bit)
access : read-write

PM124 : P12%s I/O mode select
bits : 4 - 4 (1 bit)
access : read-write


PM13

Port mode register 13
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM13 PM13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM130 PM136 PM137

PM130 : P13%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM136 : P13%s I/O mode select
bits : 6 - 12 (7 bit)
access : read-write

PM137 : P13%s I/O mode select
bits : 7 - 13 (7 bit)
access : read-write


PM14

Port mode register 14
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PM14 PM14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PM140 PM146 PM147

PM140 : P14%s I/O mode select
bits : 0 - 0 (1 bit)
access : read-write

PM146 : P14%s I/O mode select
bits : 6 - 12 (7 bit)
access : read-write

PM147 : P14%s I/O mode select
bits : 7 - 13 (7 bit)
access : read-write


P3

Port register 3
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3 P3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P30 P31

P30 : P3%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P31 : P3%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write


PU0

Pull-up resistor option register 0
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU0 PU0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU00 PU01

PU00 : P0%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU01 : P0%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PU1

Pull-up resistor option register 1
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU1 PU1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17

PU10 : P1%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU11 : P1%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write

PU12 : P1%s on-chip pull-up resistor selection
bits : 2 - 2 (1 bit)
access : read-write

PU13 : P1%s on-chip pull-up resistor selection
bits : 3 - 3 (1 bit)
access : read-write

PU14 : P1%s on-chip pull-up resistor selection
bits : 4 - 4 (1 bit)
access : read-write

PU15 : P1%s on-chip pull-up resistor selection
bits : 5 - 5 (1 bit)
access : read-write

PU16 : P1%s on-chip pull-up resistor selection
bits : 6 - 6 (1 bit)
access : read-write

PU17 : P1%s on-chip pull-up resistor selection
bits : 7 - 7 (1 bit)
access : read-write


PU2

Pull-up resistor option register 2
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU2 PU2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU20 PU21 PU22 PU23 PU24 PU25 PU26 PU27

PU20 : P2%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU21 : P2%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write

PU22 : P2%s on-chip pull-up resistor selection
bits : 2 - 2 (1 bit)
access : read-write

PU23 : P2%s on-chip pull-up resistor selection
bits : 3 - 3 (1 bit)
access : read-write

PU24 : P2%s on-chip pull-up resistor selection
bits : 4 - 4 (1 bit)
access : read-write

PU25 : P2%s on-chip pull-up resistor selection
bits : 5 - 5 (1 bit)
access : read-write

PU26 : P2%s on-chip pull-up resistor selection
bits : 6 - 6 (1 bit)
access : read-write

PU27 : P2%s on-chip pull-up resistor selection
bits : 7 - 7 (1 bit)
access : read-write


PU3

Pull-up resistor option register 3
address_offset : 0x33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU3 PU3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU30 PU31

PU30 : P3%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU31 : P3%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PU4

Pull-up resistor option register 4
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU4 PU4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU40 PU41

PU40 : P4%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU41 : P4%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PU5

Pull-up resistor option register 5
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU5 PU5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU50 PU51

PU50 : P5%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU51 : P5%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PU6

Pull-up resistor option register 6
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU6 PU6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU62 PU63

PU62 : P6%s on-chip pull-up resistor selection
bits : 2 - 4 (3 bit)
access : read-write

PU63 : P6%s on-chip pull-up resistor selection
bits : 3 - 5 (3 bit)
access : read-write


PU7

Pull-up resistor option register 7
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU7 PU7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU70 PU71 PU72 PU73 PU74 PU75

PU70 : P7%s on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU71 : P7%s on-chip pull-up resistor selection
bits : 1 - 1 (1 bit)
access : read-write

PU72 : P7%s on-chip pull-up resistor selection
bits : 2 - 2 (1 bit)
access : read-write

PU73 : P7%s on-chip pull-up resistor selection
bits : 3 - 3 (1 bit)
access : read-write

PU74 : P7%s on-chip pull-up resistor selection
bits : 4 - 4 (1 bit)
access : read-write

PU75 : P7%s on-chip pull-up resistor selection
bits : 5 - 5 (1 bit)
access : read-write


PU12

Pull-up resistor option register 12
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU12 PU12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU120

PU120 : P120 on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write


PU13

Pull-up resistor option register 13
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU13 PU13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU130 PU136 PU137

PU130 : P130 on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU136 : P13%s on-chip pull-up resistor selection
bits : 6 - 12 (7 bit)
access : read-write

PU137 : P13%s on-chip pull-up resistor selection
bits : 7 - 13 (7 bit)
access : read-write


PU14

Pull-up resistor option register 14
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PU14 PU14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PU140 PU146 PU147

PU140 : P140 on-chip pull-up resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PU146 : P14%s on-chip pull-up resistor selection
bits : 6 - 12 (7 bit)
access : read-write

PU147 : P14%s on-chip pull-up resistor selection
bits : 7 - 13 (7 bit)
access : read-write


P4

Port register 4
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4 P4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P40 P41

P40 : P4%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P41 : P4%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write


PD0

Pull-down resistor option register 0
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD0 PD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD00 PD01

PD00 : PD0%s on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD01 : PD0%s on-chip pull-down resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PD1

Pull-down resistor option register 1
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD1 PD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17

PD10 : PD1%s on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD11 : PD1%s on-chip pull-down resistor selection
bits : 1 - 1 (1 bit)
access : read-write

PD12 : PD1%s on-chip pull-down resistor selection
bits : 2 - 2 (1 bit)
access : read-write

PD13 : PD1%s on-chip pull-down resistor selection
bits : 3 - 3 (1 bit)
access : read-write

PD14 : PD1%s on-chip pull-down resistor selection
bits : 4 - 4 (1 bit)
access : read-write

PD15 : PD1%s on-chip pull-down resistor selection
bits : 5 - 5 (1 bit)
access : read-write

PD16 : PD1%s on-chip pull-down resistor selection
bits : 6 - 6 (1 bit)
access : read-write

PD17 : PD1%s on-chip pull-down resistor selection
bits : 7 - 7 (1 bit)
access : read-write


PD2

Pull-down resistor option register 2
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD2 PD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27

PD20 : PD2%s on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD21 : PD2%s on-chip pull-down resistor selection
bits : 1 - 1 (1 bit)
access : read-write

PD22 : PD2%s on-chip pull-down resistor selection
bits : 2 - 2 (1 bit)
access : read-write

PD23 : PD2%s on-chip pull-down resistor selection
bits : 3 - 3 (1 bit)
access : read-write

PD24 : PD2%s on-chip pull-down resistor selection
bits : 4 - 4 (1 bit)
access : read-write

PD25 : PD2%s on-chip pull-down resistor selection
bits : 5 - 5 (1 bit)
access : read-write

PD26 : PD2%s on-chip pull-down resistor selection
bits : 6 - 6 (1 bit)
access : read-write

PD27 : PD2%s on-chip pull-down resistor selection
bits : 7 - 7 (1 bit)
access : read-write


PD3

Pull-down resistor option register 3
address_offset : 0x43 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD3 PD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD30 PD31

PD30 : PD3%s on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD31 : PD3%s on-chip pull-down resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PD5

Pull-down resistor option register 5
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD5 PD5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD50 PD51

PD50 : PD5%s on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD51 : PD5%s on-chip pull-down resistor selection
bits : 1 - 1 (1 bit)
access : read-write


PD6

Pull-down resistor option register 6
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD6 PD6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD62 PD63

PD62 : PD0%s on-chip pull-down resistor selection
bits : 2 - 4 (3 bit)
access : read-write

PD63 : PD0%s on-chip pull-down resistor selection
bits : 3 - 5 (3 bit)
access : read-write


PD7

Pull-down resistor option register 7
address_offset : 0x47 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD7 PD7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD70 PD71 PD72 PD73 PD74 PD75

PD70 : PD7%s on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD71 : PD7%s on-chip pull-down resistor selection
bits : 1 - 1 (1 bit)
access : read-write

PD72 : PD7%s on-chip pull-down resistor selection
bits : 2 - 2 (1 bit)
access : read-write

PD73 : PD7%s on-chip pull-down resistor selection
bits : 3 - 3 (1 bit)
access : read-write

PD74 : PD7%s on-chip pull-down resistor selection
bits : 4 - 4 (1 bit)
access : read-write

PD75 : PD7%s on-chip pull-down resistor selection
bits : 5 - 5 (1 bit)
access : read-write


PD12

Pull-down resistor option register 12
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD12 PD12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD120

PD120 : PD120 on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write


PD13

Pull-down resistor option register 13
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD13 PD13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD130 PD136

PD130 : PD130 on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD136 : PD136 on-chip pull-down resistor selection
bits : 6 - 12 (7 bit)
access : read-write


PD14

Pull-down resistor option register 14
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD14 PD14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PD140 PD146 PD147

PD140 : P140 on-chip pull-down resistor selection
bits : 0 - 0 (1 bit)
access : read-write

PD146 : P14%s on-chip pull-down resistor selection
bits : 6 - 12 (7 bit)
access : read-write

PD147 : P14%s on-chip pull-down resistor selection
bits : 7 - 13 (7 bit)
access : read-write


P5

Port register 5
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5 P5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P50 P51

P50 : P5%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P51 : P5%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write


POM0

Port output mode register 0
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM0 POM0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM1

Port output mode register 1
address_offset : 0x51 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM1 POM1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM2

Port output mode register 2
address_offset : 0x52 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM2 POM2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM3

Port output mode register 3
address_offset : 0x53 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM3 POM3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM4

Port output mode register 4
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM4 POM4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM5

Port output mode register 5
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM5 POM5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM6

Port output mode register 6
address_offset : 0x56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM6 POM6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM7

Port output mode register 7
address_offset : 0x57 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM7 POM7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM12

Port output mode register 12
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM12 POM12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM13

Port output mode register 13
address_offset : 0x5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM13 POM13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

POM14

Port output mode register 14
address_offset : 0x5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POM14 POM14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

P6

Port register 6
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6 P6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P60 P61 P62 P63

P60 : P6%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P61 : P6%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write

P62 : P6%s input/output data register
bits : 2 - 2 (1 bit)
access : read-write

P63 : P6%s input/output data register
bits : 3 - 3 (1 bit)
access : read-write


PMC0

Port mode control register 0
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC0 PMC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC1

Port mode control register 1
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC1 PMC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC2

Port mode control register 2
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC2 PMC2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC3

Port mode control register 3
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC3 PMC3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC5

Port mode control register 5
address_offset : 0x65 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC5 PMC5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC6

Port mode control register 6
address_offset : 0x66 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC6 PMC6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC7

Port mode control register 7
address_offset : 0x67 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC7 PMC7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC12

Port mode control register 12
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC12 PMC12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC13

Port mode control register 13
address_offset : 0x6D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC13 PMC13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PMC14

Port mode control register 14
address_offset : 0x6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMC14 PMC14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

P7

Port register 7
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7 P7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P70 P71 P72 P73 P74 P75

P70 : P7%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P71 : P7%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write

P72 : P7%s input/output data register
bits : 2 - 2 (1 bit)
access : read-write

P73 : P7%s input/output data register
bits : 3 - 3 (1 bit)
access : read-write

P74 : P7%s input/output data register
bits : 4 - 4 (1 bit)
access : read-write

P75 : P7%s input/output data register
bits : 5 - 5 (1 bit)
access : read-write


PCLR0

Port clear register 0
address_offset : 0x70 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR0 PCLR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR1

Port clear register 1
address_offset : 0x71 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR1 PCLR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR2

Port clear register 2
address_offset : 0x72 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR2 PCLR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR3

Port clear register 3
address_offset : 0x73 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR3 PCLR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR4

Port clear register 4
address_offset : 0x74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR4 PCLR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR5

Port clear register 5
address_offset : 0x75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR5 PCLR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR6

Port clear register 6
address_offset : 0x76 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR6 PCLR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR7

Port clear register 7
address_offset : 0x77 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR7 PCLR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR12

Port clear register 12
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR12 PCLR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR13

Port clear register 13
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR13 PCLR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCLR14

Port clear register 14
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLR14 PCLR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

P00CFG

Alterate Output Function configuration register
address_offset : 0x800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P00CFG P00CFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG : Alterate Output Function configuration register
bits : 0 - 3 (4 bit)

Enumeration:

0x00 : GPIO

Port used as GPIO

0x01 : TO10

Port used as TO10

0x02 : TO11

Port used as TO11

0x03 : TO12

Port used as TO12

0x04 : TO13

Port used as TO13

0x05 : SDO00/TxD0

Port used as SDO00/TxD0

0x06 : SDO20/TxD2

Port used as SDO20/TxD2

0x07 : CLKBUZ0

Port used as CLKBUZ0

0x08 : SCLKO00

Port used as SCLK00 output

0x09 : SCLKO20

Port used as SCLK20 output

0x0A : TXD1

Port used as TXD1

End of enumeration elements list.


P01CFG


address_offset : 0x801 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P01CFG P01CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P10CFG


address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P10CFG P10CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P11CFG


address_offset : 0x809 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P11CFG P11CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P12CFG


address_offset : 0x80A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P12CFG P12CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P13CFG


address_offset : 0x80B Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P13CFG P13CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P14CFG


address_offset : 0x80C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P14CFG P14CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P15CFG


address_offset : 0x80D Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P15CFG P15CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P16CFG


address_offset : 0x80E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P16CFG P16CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P17CFG


address_offset : 0x80F Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P17CFG P17CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P20CFG


address_offset : 0x810 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P20CFG P20CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P21CFG


address_offset : 0x811 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P21CFG P21CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P22CFG


address_offset : 0x812 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P22CFG P22CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P23CFG


address_offset : 0x813 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P23CFG P23CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P24CFG


address_offset : 0x814 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P24CFG P24CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P25CFG


address_offset : 0x815 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P25CFG P25CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P26CFG


address_offset : 0x816 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P26CFG P26CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P27CFG


address_offset : 0x817 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P27CFG P27CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P30CFG


address_offset : 0x818 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P30CFG P30CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P31CFG


address_offset : 0x819 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P31CFG P31CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P40CFG


address_offset : 0x820 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P40CFG P40CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P41CFG


address_offset : 0x821 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P41CFG P41CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P50CFG


address_offset : 0x828 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P50CFG P50CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P51CFG


address_offset : 0x829 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P51CFG P51CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P60CFG


address_offset : 0x830 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P60CFG P60CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P61CFG


address_offset : 0x831 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P61CFG P61CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P62CFG


address_offset : 0x832 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P62CFG P62CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P63CFG


address_offset : 0x833 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P63CFG P63CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P70CFG


address_offset : 0x838 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P70CFG P70CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P71CFG


address_offset : 0x839 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P71CFG P71CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P72CFG


address_offset : 0x83A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P72CFG P72CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P73CFG


address_offset : 0x83B Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P73CFG P73CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P74CFG


address_offset : 0x83C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P74CFG P74CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P75CFG


address_offset : 0x83D Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P75CFG P75CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P120CFG


address_offset : 0x840 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P120CFG P120CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P121CFG


address_offset : 0x841 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P121CFG P121CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P122CFG


address_offset : 0x842 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P122CFG P122CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P123CFG


address_offset : 0x843 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P123CFG P123CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P124CFG


address_offset : 0x844 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P124CFG P124CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P130CFG


address_offset : 0x848 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P130CFG P130CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P136CFG


address_offset : 0x84E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P136CFG P136CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P137CFG


address_offset : 0x84F Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P137CFG P137CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P140CFG


address_offset : 0x850 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P140CFG P140CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P146CFG


address_offset : 0x856 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P146CFG P146CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P147CFG


address_offset : 0x857 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P147CFG P147CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TI10PCFG

TI10 alternate function pin configuration register
address_offset : 0x860 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TI10PCFG TI10PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as TI10

0x02 : P01

P01 used as TI10

0x03 : P10

P10 used as TI10

0x04 : P11

P11 used as TI10

0x05 : P12

P12 used as TI10

0x06 : P13

P13 used as TI10

0x07 : P14

P14 used as TI10

0x08 : P15

P15 used as TI10

0x09 : P16

P16 used as TI10

0x0A : P17

P17 used as TI10

0x0B : P20

P20 used as TI10

0x0C : P21

P21 used as TI10

0x0D : P22

P22 used as TI10

0x0E : P23

P23 used as TI10

0x0F : P24

P24 used as TI10

0x10 : P25

P25 used as TI10

0x11 : P26

P26 used as TI10

0x12 : P27

P27 used as TI10

0x13 : P30

P30 used as TI10

0x14 : P31

P31 used as TI10

0x15 : P40

P40 used as TI10

0x16 : P41

P41 used as TI10

0x17 : P50

P50 used as TI10

0x18 : P51

P51 used as TI10

0x19 : P60

P60 used as TI10

0x1A : P61

P61 used as TI10

0x1B : P62

P62 used as TI10

0x1C : P63

P63 used as TI10

0x1D : P70

P70 used as TI10

0x1E : P71

P71 used as TI10

0x1F : P72

P72 used as TI10

0x20 : P73

P73 used as TI10

0x21 : P74

P74 used as TI10

0x22 : P75

P75 used as TI10

0x23 : P120

P120 used as TI10

0x24 : P121

P121 used as TI10

0x25 : P122

P122 used as TI10

0x26 : P123

P123 used as TI10

0x27 : P124

P124 used as TI10

0x28 : P130

P130 used as TI10

0x29 : P136

P136 used as TI10

0x2A : P137

P137 used as TI10

0x2B : P140

P140 used as TI10

0x2C : P146

P146 used as TI10

0x2D : P147

P147 used as TI10

End of enumeration elements list.


TI11PCFG

TI11 alternate function pin configuration register
address_offset : 0x861 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TI11PCFG TI11PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as TI11

0x02 : P01

P01 used as TI11

0x03 : P10

P10 used as TI11

0x04 : P11

P11 used as TI11

0x05 : P12

P12 used as TI11

0x06 : P13

P13 used as TI11

0x07 : P14

P14 used as TI11

0x08 : P15

P15 used as TI11

0x09 : P16

P16 used as TI11

0x0A : P17

P17 used as TI11

0x0B : P20

P20 used as TI11

0x0C : P21

P21 used as TI11

0x0D : P22

P22 used as TI11

0x0E : P23

P23 used as TI11

0x0F : P24

P24 used as TI11

0x10 : P25

P25 used as TI11

0x11 : P26

P26 used as TI11

0x12 : P27

P27 used as TI11

0x13 : P30

P30 used as TI11

0x14 : P31

P31 used as TI11

0x15 : P40

P40 used as TI11

0x16 : P41

P41 used as TI11

0x17 : P50

P50 used as TI11

0x18 : P51

P51 used as TI11

0x19 : P60

P60 used as TI11

0x1A : P61

P61 used as TI11

0x1B : P62

P62 used as TI11

0x1C : P63

P63 used as TI11

0x1D : P70

P70 used as TI11

0x1E : P71

P71 used as TI11

0x1F : P72

P72 used as TI11

0x20 : P73

P73 used as TI11

0x21 : P74

P74 used as TI11

0x22 : P75

P75 used as TI11

0x23 : P120

P120 used as TI11

0x24 : P121

P121 used as TI11

0x25 : P122

P122 used as TI11

0x26 : P123

P123 used as TI11

0x27 : P124

P124 used as TI11

0x28 : P130

P130 used as TI11

0x29 : P136

P136 used as TI11

0x2A : P137

P137 used as TI11

0x2B : P140

P140 used as TI11

0x2C : P146

P146 used as TI11

0x2D : P147

P147 used as TI11

End of enumeration elements list.


TI12PCFG

TI12 alternate function pin configuration register
address_offset : 0x862 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TI12PCFG TI12PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as TI12

0x02 : P01

P01 used as TI12

0x03 : P10

P10 used as TI12

0x04 : P11

P11 used as TI12

0x05 : P12

P12 used as TI12

0x06 : P13

P13 used as TI12

0x07 : P14

P14 used as TI12

0x08 : P15

P15 used as TI12

0x09 : P16

P16 used as TI12

0x0A : P17

P17 used as TI12

0x0B : P20

P20 used as TI12

0x0C : P21

P21 used as TI12

0x0D : P22

P22 used as TI12

0x0E : P23

P23 used as TI12

0x0F : P24

P24 used as TI12

0x10 : P25

P25 used as TI12

0x11 : P26

P26 used as TI12

0x12 : P27

P27 used as TI12

0x13 : P30

P30 used as TI12

0x14 : P31

P31 used as TI12

0x15 : P40

P40 used as TI12

0x16 : P41

P41 used as TI12

0x17 : P50

P50 used as TI12

0x18 : P51

P51 used as TI12

0x19 : P60

P60 used as TI12

0x1A : P61

P61 used as TI12

0x1B : P62

P62 used as TI12

0x1C : P63

P63 used as TI12

0x1D : P70

P70 used as TI12

0x1E : P71

P71 used as TI12

0x1F : P72

P72 used as TI12

0x20 : P73

P73 used as TI12

0x21 : P74

P74 used as TI12

0x22 : P75

P75 used as TI12

0x23 : P120

P120 used as TI12

0x24 : P121

P121 used as TI12

0x25 : P122

P122 used as TI12

0x26 : P123

P123 used as TI12

0x27 : P124

P124 used as TI12

0x28 : P130

P130 used as TI12

0x29 : P136

P136 used as TI12

0x2A : P137

P137 used as TI12

0x2B : P140

P140 used as TI12

0x2C : P146

P146 used as TI12

0x2D : P147

P147 used as TI12

End of enumeration elements list.


TI13PCFG

TI13 alternate function pin configuration register
address_offset : 0x863 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TI13PCFG TI13PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as TI13

0x02 : P01

P01 used as TI13

0x03 : P10

P10 used as TI13

0x04 : P11

P11 used as TI13

0x05 : P12

P12 used as TI13

0x06 : P13

P13 used as TI13

0x07 : P14

P14 used as TI13

0x08 : P15

P15 used as TI13

0x09 : P16

P16 used as TI13

0x0A : P17

P17 used as TI13

0x0B : P20

P20 used as TI13

0x0C : P21

P21 used as TI13

0x0D : P22

P22 used as TI13

0x0E : P23

P23 used as TI13

0x0F : P24

P24 used as TI13

0x10 : P25

P25 used as TI13

0x11 : P26

P26 used as TI13

0x12 : P27

P27 used as TI13

0x13 : P30

P30 used as TI13

0x14 : P31

P31 used as TI13

0x15 : P40

P40 used as TI13

0x16 : P41

P41 used as TI13

0x17 : P50

P50 used as TI13

0x18 : P51

P51 used as TI13

0x19 : P60

P60 used as TI13

0x1A : P61

P61 used as TI13

0x1B : P62

P62 used as TI13

0x1C : P63

P63 used as TI13

0x1D : P70

P70 used as TI13

0x1E : P71

P71 used as TI13

0x1F : P72

P72 used as TI13

0x20 : P73

P73 used as TI13

0x21 : P74

P74 used as TI13

0x22 : P75

P75 used as TI13

0x23 : P120

P120 used as TI13

0x24 : P121

P121 used as TI13

0x25 : P122

P122 used as TI13

0x26 : P123

P123 used as TI13

0x27 : P124

P124 used as TI13

0x28 : P130

P130 used as TI13

0x29 : P136

P136 used as TI13

0x2A : P137

P137 used as TI13

0x2B : P140

P140 used as TI13

0x2C : P146

P146 used as TI13

0x2D : P147

P147 used as TI13

End of enumeration elements list.


INTP0PCFG

INTP0 alternate function pin configuration register
address_offset : 0x864 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTP0PCFG INTP0PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as INTP0

0x02 : P01

P01 used as INTP0

0x03 : P10

P10 used as INTP0

0x04 : P11

P11 used as INTP0

0x05 : P12

P12 used as INTP0

0x06 : P13

P13 used as INTP0

0x07 : P14

P14 used as INTP0

0x08 : P15

P15 used as INTP0

0x09 : P16

P16 used as INTP0

0x0A : P17

P17 used as INTP0

0x0B : P20

P20 used as INTP0

0x0C : P21

P21 used as INTP0

0x0D : P22

P22 used as INTP0

0x0E : P23

P23 used as INTP0

0x0F : P24

P24 used as INTP0

0x10 : P25

P25 used as INTP0

0x11 : P26

P26 used as INTP0

0x12 : P27

P27 used as INTP0

0x13 : P30

P30 used as INTP0

0x14 : P31

P31 used as INTP0

0x15 : P40

P40 used as INTP0

0x16 : P41

P41 used as INTP0

0x17 : P50

P50 used as INTP0

0x18 : P51

P51 used as INTP0

0x19 : P60

P60 used as INTP0

0x1A : P61

P61 used as INTP0

0x1B : P62

P62 used as INTP0

0x1C : P63

P63 used as INTP0

0x1D : P70

P70 used as INTP0

0x1E : P71

P71 used as INTP0

0x1F : P72

P72 used as INTP0

0x20 : P73

P73 used as INTP0

0x21 : P74

P74 used as INTP0

0x22 : P75

P75 used as INTP0

0x23 : P120

P120 used as INTP0

0x24 : P121

P121 used as INTP0

0x25 : P122

P122 used as INTP0

0x26 : P123

P123 used as INTP0

0x27 : P124

P124 used as INTP0

0x28 : P130

P130 used as INTP0

0x29 : P136

P136 used as INTP0

0x2A : P137

P137 used as INTP0

0x2B : P140

P140 used as INTP0

0x2C : P146

P146 used as INTP0

0x2D : P147

P147 used as INTP0

End of enumeration elements list.


INTP1PCFG

INTP1 alternate function pin configuration register
address_offset : 0x865 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTP1PCFG INTP1PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as INTP1

0x02 : P01

P01 used as INTP1

0x03 : P10

P10 used as INTP1

0x04 : P11

P11 used as INTP1

0x05 : P12

P12 used as INTP1

0x06 : P13

P13 used as INTP1

0x07 : P14

P14 used as INTP1

0x08 : P15

P15 used as INTP1

0x09 : P16

P16 used as INTP1

0x0A : P17

P17 used as INTP1

0x0B : P20

P20 used as INTP1

0x0C : P21

P21 used as INTP1

0x0D : P22

P22 used as INTP1

0x0E : P23

P23 used as INTP1

0x0F : P24

P24 used as INTP1

0x10 : P25

P25 used as INTP1

0x11 : P26

P26 used as INTP1

0x12 : P27

P27 used as INTP1

0x13 : P30

P30 used as INTP1

0x14 : P31

P31 used as INTP1

0x15 : P40

P40 used as INTP1

0x16 : P41

P41 used as INTP1

0x17 : P50

P50 used as INTP1

0x18 : P51

P51 used as INTP1

0x19 : P60

P60 used as INTP1

0x1A : P61

P61 used as INTP1

0x1B : P62

P62 used as INTP1

0x1C : P63

P63 used as INTP1

0x1D : P70

P70 used as INTP1

0x1E : P71

P71 used as INTP1

0x1F : P72

P72 used as INTP1

0x20 : P73

P73 used as INTP1

0x21 : P74

P74 used as INTP1

0x22 : P75

P75 used as INTP1

0x23 : P120

P120 used as INTP1

0x24 : P121

P121 used as INTP1

0x25 : P122

P122 used as INTP1

0x26 : P123

P123 used as INTP1

0x27 : P124

P124 used as INTP1

0x28 : P130

P130 used as INTP1

0x29 : P136

P136 used as INTP1

0x2A : P137

P137 used as INTP1

0x2B : P140

P140 used as INTP1

0x2C : P146

P146 used as INTP1

0x2D : P147

P147 used as INTP1

End of enumeration elements list.


INTP2PCFG

INTP2 alternate function pin configuration register
address_offset : 0x866 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTP2PCFG INTP2PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as INTP2

0x02 : P01

P01 used as INTP2

0x03 : P10

P10 used as INTP2

0x04 : P11

P11 used as INTP2

0x05 : P12

P12 used as INTP2

0x06 : P13

P13 used as INTP2

0x07 : P14

P14 used as INTP2

0x08 : P15

P15 used as INTP2

0x09 : P16

P16 used as INTP2

0x0A : P17

P17 used as INTP2

0x0B : P20

P20 used as INTP2

0x0C : P21

P21 used as INTP2

0x0D : P22

P22 used as INTP2

0x0E : P23

P23 used as INTP2

0x0F : P24

P24 used as INTP2

0x10 : P25

P25 used as INTP2

0x11 : P26

P26 used as INTP2

0x12 : P27

P27 used as INTP2

0x13 : P30

P30 used as INTP2

0x14 : P31

P31 used as INTP2

0x15 : P40

P40 used as INTP2

0x16 : P41

P41 used as INTP2

0x17 : P50

P50 used as INTP2

0x18 : P51

P51 used as INTP2

0x19 : P60

P60 used as INTP2

0x1A : P61

P61 used as INTP2

0x1B : P62

P62 used as INTP2

0x1C : P63

P63 used as INTP2

0x1D : P70

P70 used as INTP2

0x1E : P71

P71 used as INTP2

0x1F : P72

P72 used as INTP2

0x20 : P73

P73 used as INTP2

0x21 : P74

P74 used as INTP2

0x22 : P75

P75 used as INTP2

0x23 : P120

P120 used as INTP2

0x24 : P121

P121 used as INTP2

0x25 : P122

P122 used as INTP2

0x26 : P123

P123 used as INTP2

0x27 : P124

P124 used as INTP2

0x28 : P130

P130 used as INTP2

0x29 : P136

P136 used as INTP2

0x2A : P137

P137 used as INTP2

0x2B : P140

P140 used as INTP2

0x2C : P146

P146 used as INTP2

0x2D : P147

P147 used as INTP2

End of enumeration elements list.


INTP3PCFG

INTP3 alternate function pin configuration register
address_offset : 0x867 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTP3PCFG INTP3PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as INTP3

0x02 : P01

P01 used as INTP3

0x03 : P10

P10 used as INTP3

0x04 : P11

P11 used as INTP3

0x05 : P12

P12 used as INTP3

0x06 : P13

P13 used as INTP3

0x07 : P14

P14 used as INTP3

0x08 : P15

P15 used as INTP3

0x09 : P16

P16 used as INTP3

0x0A : P17

P17 used as INTP3

0x0B : P20

P20 used as INTP3

0x0C : P21

P21 used as INTP3

0x0D : P22

P22 used as INTP3

0x0E : P23

P23 used as INTP3

0x0F : P24

P24 used as INTP3

0x10 : P25

P25 used as INTP3

0x11 : P26

P26 used as INTP3

0x12 : P27

P27 used as INTP3

0x13 : P30

P30 used as INTP3

0x14 : P31

P31 used as INTP3

0x15 : P40

P40 used as INTP3

0x16 : P41

P41 used as INTP3

0x17 : P50

P50 used as INTP3

0x18 : P51

P51 used as INTP3

0x19 : P60

P60 used as INTP3

0x1A : P61

P61 used as INTP3

0x1B : P62

P62 used as INTP3

0x1C : P63

P63 used as INTP3

0x1D : P70

P70 used as INTP3

0x1E : P71

P71 used as INTP3

0x1F : P72

P72 used as INTP3

0x20 : P73

P73 used as INTP3

0x21 : P74

P74 used as INTP3

0x22 : P75

P75 used as INTP3

0x23 : P120

P120 used as INTP3

0x24 : P121

P121 used as INTP3

0x25 : P122

P122 used as INTP3

0x26 : P123

P123 used as INTP3

0x27 : P124

P124 used as INTP3

0x28 : P130

P130 used as INTP3

0x29 : P136

P136 used as INTP3

0x2A : P137

P137 used as INTP3

0x2B : P140

P140 used as INTP3

0x2C : P146

P146 used as INTP3

0x2D : P147

P147 used as INTP3

End of enumeration elements list.


SDI00PCFG

SDI00/RXD0/SDA00 alternate function pin configuration register
address_offset : 0x868 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDI00PCFG SDI00PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SDI00/RXD0/SDA00

0x02 : P01

P01 used as SDI00/RXD0/SDA00

0x03 : P10

P10 used as SDI00/RXD0/SDA00

0x04 : P11

P11 used as SDI00/RXD0/SDA00

0x05 : P12

P12 used as SDI00/RXD0/SDA00

0x06 : P13

P13 used as SDI00/RXD0/SDA00

0x07 : P14

P14 used as SDI00/RXD0/SDA00

0x08 : P15

P15 used as SDI00/RXD0/SDA00

0x09 : P16

P16 used as SDI00/RXD0/SDA00

0x0A : P17

P17 used as SDI00/RXD0/SDA00

0x0B : P20

P20 used as SDI00/RXD0/SDA00

0x0C : P21

P21 used as SDI00/RXD0/SDA00

0x0D : P22

P22 used as SDI00/RXD0/SDA00

0x0E : P23

P23 used as SDI00/RXD0/SDA00

0x0F : P24

P24 used as SDI00/RXD0/SDA00

0x10 : P25

P25 used as SDI00/RXD0/SDA00

0x11 : P26

P26 used as SDI00/RXD0/SDA00

0x12 : P27

P27 used as SDI00/RXD0/SDA00

0x13 : P30

P30 used as SDI00/RXD0/SDA00

0x14 : P31

P31 used as SDI00/RXD0/SDA00

0x15 : P40

P40 used as SDI00/RXD0/SDA00

0x16 : P41

P41 used as SDI00/RXD0/SDA00

0x17 : P50

P50 used as SDI00/RXD0/SDA00

0x18 : P51

P51 used as SDI00/RXD0/SDA00

0x19 : P60

P60 used as SDI00/RXD0/SDA00

0x1A : P61

P61 used as SDI00/RXD0/SDA00

0x1B : P62

P62 used as SDI00/RXD0/SDA00

0x1C : P63

P63 used as SDI00/RXD0/SDA00

0x1D : P70

P70 used as SDI00/RXD0/SDA00

0x1E : P71

P71 used as SDI00/RXD0/SDA00

0x1F : P72

P72 used as SDI00/RXD0/SDA00

0x20 : P73

P73 used as SDI00/RXD0/SDA00

0x21 : P74

P74 used as SDI00/RXD0/SDA00

0x22 : P75

P75 used as SDI00/RXD0/SDA00

0x23 : P120

P120 used as SDI00/RXD0/SDA00

0x24 : P121

P121 used as SDI00/RXD0/SDA00

0x25 : P122

P122 used as SDI00/RXD0/SDA00

0x26 : P123

P123 used as SDI00/RXD0/SDA00

0x27 : P124

P124 used as SDI00/RXD0/SDA00

0x28 : P130

P130 used as SDI00/RXD0/SDA00

0x29 : P136

P136 used as SDI00/RXD0/SDA00

0x2A : P137

P137 used as SDI00/RXD0/SDA00

0x2B : P140

P140 used as SDI00/RXD0/SDA00

0x2C : P146

P146 used as SDI00/RXD0/SDA00

0x2D : P147

P147 used as SDI00/RXD0/SDA00

End of enumeration elements list.


SDA00PCFG

SDI00/RXD0/SDA00 alternate function pin configuration register
address_offset : 0x868 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : SDI00PCFG
reset_Mask : 0x0

SDA00PCFG SDA00PCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXD0PCFG

SDI00/RXD0/SDA00 alternate function pin configuration register
address_offset : 0x868 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : SDI00PCFG
reset_Mask : 0x0

RXD0PCFG RXD0PCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCLKI00PCFG

SCLKI00 alternate function pin configuration register
address_offset : 0x869 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLKI00PCFG SCLKI00PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SCLKI00

0x02 : P01

P01 used as SCLKI00

0x03 : P10

P10 used as SCLKI00

0x04 : P11

P11 used as SCLKI00

0x05 : P12

P12 used as SCLKI00

0x06 : P13

P13 used as SCLKI00

0x07 : P14

P14 used as SCLKI00

0x08 : P15

P15 used as SCLKI00

0x09 : P16

P16 used as SCLKI00

0x0A : P17

P17 used as SCLKI00

0x0B : P20

P20 used as SCLKI00

0x0C : P21

P21 used as SCLKI00

0x0D : P22

P22 used as SCLKI00

0x0E : P23

P23 used as SCLKI00

0x0F : P24

P24 used as SCLKI00

0x10 : P25

P25 used as SCLKI00

0x11 : P26

P26 used as SCLKI00

0x12 : P27

P27 used as SCLKI00

0x13 : P30

P30 used as SCLKI00

0x14 : P31

P31 used as SCLKI00

0x15 : P40

P40 used as SCLKI00

0x16 : P41

P41 used as SCLKI00

0x17 : P50

P50 used as SCLKI00

0x18 : P51

P51 used as SCLKI00

0x19 : P60

P60 used as SCLKI00

0x1A : P61

P61 used as SCLKI00

0x1B : P62

P62 used as SCLKI00

0x1C : P63

P63 used as SCLKI00

0x1D : P70

P70 used as SCLKI00

0x1E : P71

P71 used as SCLKI00

0x1F : P72

P72 used as SCLKI00

0x20 : P73

P73 used as SCLKI00

0x21 : P74

P74 used as SCLKI00

0x22 : P75

P75 used as SCLKI00

0x23 : P120

P120 used as SCLKI00

0x24 : P121

P121 used as SCLKI00

0x25 : P122

P122 used as SCLKI00

0x26 : P123

P123 used as SCLKI00

0x27 : P124

P124 used as SCLKI00

0x28 : P130

P130 used as SCLKI00

0x29 : P136

P136 used as SCLKI00

0x2A : P137

P137 used as SCLKI00

0x2B : P140

P140 used as SCLKI00

0x2C : P146

P146 used as SCLKI00

0x2D : P147

P147 used as SCLKI00

End of enumeration elements list.


SS00PCFG

SS00 alternate function pin configuration register
address_offset : 0x86A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SS00PCFG SS00PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SS00

0x02 : P01

P01 used as SS00

0x03 : P10

P10 used as SS00

0x04 : P11

P11 used as SS00

0x05 : P12

P12 used as SS00

0x06 : P13

P13 used as SS00

0x07 : P14

P14 used as SS00

0x08 : P15

P15 used as SS00

0x09 : P16

P16 used as SS00

0x0A : P17

P17 used as SS00

0x0B : P20

P20 used as SS00

0x0C : P21

P21 used as SS00

0x0D : P22

P22 used as SS00

0x0E : P23

P23 used as SS00

0x0F : P24

P24 used as SS00

0x10 : P25

P25 used as SS00

0x11 : P26

P26 used as SS00

0x12 : P27

P27 used as SS00

0x13 : P30

P30 used as SS00

0x14 : P31

P31 used as SS00

0x15 : P40

P40 used as SS00

0x16 : P41

P41 used as SS00

0x17 : P50

P50 used as SS00

0x18 : P51

P51 used as SS00

0x19 : P60

P60 used as SS00

0x1A : P61

P61 used as SS00

0x1B : P62

P62 used as SS00

0x1C : P63

P63 used as SS00

0x1D : P70

P70 used as SS00

0x1E : P71

P71 used as SS00

0x1F : P72

P72 used as SS00

0x20 : P73

P73 used as SS00

0x21 : P74

P74 used as SS00

0x22 : P75

P75 used as SS00

0x23 : P120

P120 used as SS00

0x24 : P121

P121 used as SS00

0x25 : P122

P122 used as SS00

0x26 : P123

P123 used as SS00

0x27 : P124

P124 used as SS00

0x28 : P130

P130 used as SS00

0x29 : P136

P136 used as SS00

0x2A : P137

P137 used as SS00

0x2B : P140

P140 used as SS00

0x2C : P146

P146 used as SS00

0x2D : P147

P147 used as SS00

End of enumeration elements list.


SDI20PCFG

SDI20/RXD2/IrRXD alternate function pin configuration register
address_offset : 0x86B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDI20PCFG SDI20PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SDI20/RXD2/IrRXD

0x02 : P01

P01 used as SDI20/RXD2/IrRXD

0x03 : P10

P10 used as SDI20/RXD2/IrRXD

0x04 : P11

P11 used as SDI20/RXD2/IrRXD

0x05 : P12

P12 used as SDI20/RXD2/IrRXD

0x06 : P13

P13 used as SDI20/RXD2/IrRXD

0x07 : P14

P14 used as SDI20/RXD2/IrRXD

0x08 : P15

P15 used as SDI20/RXD2/IrRXD

0x09 : P16

P16 used as SDI20/RXD2/IrRXD

0x0A : P17

P17 used as SDI20/RXD2/IrRXD

0x0B : P20

P20 used as SDI20/RXD2/IrRXD

0x0C : P21

P21 used as SDI20/RXD2/IrRXD

0x0D : P22

P22 used as SDI20/RXD2/IrRXD

0x0E : P23

P23 used as SDI20/RXD2/IrRXD

0x0F : P24

P24 used as SDI20/RXD2/IrRXD

0x10 : P25

P25 used as SDI20/RXD2/IrRXD

0x11 : P26

P26 used as SDI20/RXD2/IrRXD

0x12 : P27

P27 used as SDI20/RXD2/IrRXD

0x13 : P30

P30 used as SDI20/RXD2/IrRXD

0x14 : P31

P31 used as SDI20/RXD2/IrRXD

0x15 : P40

P40 used as SDI20/RXD2/IrRXD

0x16 : P41

P41 used as SDI20/RXD2/IrRXD

0x17 : P50

P50 used as SDI20/RXD2/IrRXD

0x18 : P51

P51 used as SDI20/RXD2/IrRXD

0x19 : P60

P60 used as SDI20/RXD2/IrRXD

0x1A : P61

P61 used as SDI20/RXD2/IrRXD

0x1B : P62

P62 used as SDI20/RXD2/IrRXD

0x1C : P63

P63 used as SDI20/RXD2/IrRXD

0x1D : P70

P70 used as SDI20/RXD2/IrRXD

0x1E : P71

P71 used as SDI20/RXD2/IrRXD

0x1F : P72

P72 used as SDI20/RXD2/IrRXD

0x20 : P73

P73 used as SDI20/RXD2/IrRXD

0x21 : P74

P74 used as SDI20/RXD2/IrRXD

0x22 : P75

P75 used as SDI20/RXD2/IrRXD

0x23 : P120

P120 used as SDI20/RXD2/IrRXD

0x24 : P121

P121 used as SDI20/RXD2/IrRXD

0x25 : P122

P122 used as SDI20/RXD2/IrRXD

0x26 : P123

P123 used as SDI20/RXD2/IrRXD

0x27 : P124

P124 used as SDI20/RXD2/IrRXD

0x28 : P130

P130 used as SDI20/RXD2/IrRXD

0x29 : P136

P136 used as SDI20/RXD2/IrRXD

0x2A : P137

P137 used as SDI20/RXD2/IrRXD

0x2B : P140

P140 used as SDI20/RXD2/IrRXD

0x2C : P146

P146 used as SDI20/RXD2/IrRXD

0x2D : P147

P147 used as SDI20/RXD2/IrRXD

End of enumeration elements list.


IRRXDPCFG

SDI20/RXD2/IrRXD alternate function pin configuration register
address_offset : 0x86B Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : SDI20PCFG
reset_Mask : 0x0

IRRXDPCFG IRRXDPCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXD2PCFG

SDI20/RXD2/IrRXD alternate function pin configuration register
address_offset : 0x86B Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : SDI20PCFG
reset_Mask : 0x0

RXD2PCFG RXD2PCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCLKI20PCFG

SCLKI20 alternate function pin configuration register
address_offset : 0x86C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLKI20PCFG SCLKI20PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SCLKI20

0x02 : P01

P01 used as SCLKI20

0x03 : P10

P10 used as SCLKI20

0x04 : P11

P11 used as SCLKI20

0x05 : P12

P12 used as SCLKI20

0x06 : P13

P13 used as SCLKI20

0x07 : P14

P14 used as SCLKI20

0x08 : P15

P15 used as SCLKI20

0x09 : P16

P16 used as SCLKI20

0x0A : P17

P17 used as SCLKI20

0x0B : P20

P20 used as SCLKI20

0x0C : P21

P21 used as SCLKI20

0x0D : P22

P22 used as SCLKI20

0x0E : P23

P23 used as SCLKI20

0x0F : P24

P24 used as SCLKI20

0x10 : P25

P25 used as SCLKI20

0x11 : P26

P26 used as SCLKI20

0x12 : P27

P27 used as SCLKI20

0x13 : P30

P30 used as SCLKI20

0x14 : P31

P31 used as SCLKI20

0x15 : P40

P40 used as SCLKI20

0x16 : P41

P41 used as SCLKI20

0x17 : P50

P50 used as SCLKI20

0x18 : P51

P51 used as SCLKI20

0x19 : P60

P60 used as SCLKI20

0x1A : P61

P61 used as SCLKI20

0x1B : P62

P62 used as SCLKI20

0x1C : P63

P63 used as SCLKI20

0x1D : P70

P70 used as SCLKI20

0x1E : P71

P71 used as SCLKI20

0x1F : P72

P72 used as SCLKI20

0x20 : P73

P73 used as SCLKI20

0x21 : P74

P74 used as SCLKI20

0x22 : P75

P75 used as SCLKI20

0x23 : P120

P120 used as SCLKI20

0x24 : P121

P121 used as SCLKI20

0x25 : P122

P122 used as SCLKI20

0x26 : P123

P123 used as SCLKI20

0x27 : P124

P124 used as SCLKI20

0x28 : P130

P130 used as SCLKI20

0x29 : P136

P136 used as SCLKI20

0x2A : P137

P137 used as SCLKI20

0x2B : P140

P140 used as SCLKI20

0x2C : P146

P146 used as SCLKI20

0x2D : P147

P147 used as SCLKI20

End of enumeration elements list.


SDAA0PCFG

SDAA0 alternate function pin configuration register
address_offset : 0x86D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDAA0PCFG SDAA0PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SDAA0

0x02 : P01

P01 used as SDAA0

0x03 : P10

P10 used as SDAA0

0x04 : P11

P11 used as SDAA0

0x05 : P12

P12 used as SDAA0

0x06 : P13

P13 used as SDAA0

0x07 : P14

P14 used as SDAA0

0x08 : P15

P15 used as SDAA0

0x09 : P16

P16 used as SDAA0

0x0A : P17

P17 used as SDAA0

0x0B : P20

P20 used as SDAA0

0x0C : P21

P21 used as SDAA0

0x0D : P22

P22 used as SDAA0

0x0E : P23

P23 used as SDAA0

0x0F : P24

P24 used as SDAA0

0x10 : P25

P25 used as SDAA0

0x11 : P26

P26 used as SDAA0

0x12 : P27

P27 used as SDAA0

0x13 : P30

P30 used as SDAA0

0x14 : P31

P31 used as SDAA0

0x15 : P40

P40 used as SDAA0

0x16 : P41

P41 used as SDAA0

0x17 : P50

P50 used as SDAA0

0x18 : P51

P51 used as SDAA0

0x19 : P60

P60 used as SDAA0

0x1A : P61

P61 used as SDAA0

0x1B : P62

P62 used as SDAA0

0x1C : P63

P63 used as SDAA0

0x1D : P70

P70 used as SDAA0

0x1E : P71

P71 used as SDAA0

0x1F : P72

P72 used as SDAA0

0x20 : P73

P73 used as SDAA0

0x21 : P74

P74 used as SDAA0

0x22 : P75

P75 used as SDAA0

0x23 : P120

P120 used as SDAA0

0x24 : P121

P121 used as SDAA0

0x25 : P122

P122 used as SDAA0

0x26 : P123

P123 used as SDAA0

0x27 : P124

P124 used as SDAA0

0x28 : P130

P130 used as SDAA0

0x29 : P136

P136 used as SDAA0

0x2A : P137

P137 used as SDAA0

0x2B : P140

P140 used as SDAA0

0x2C : P146

P146 used as SDAA0

0x2D : P147

P147 used as SDAA0

End of enumeration elements list.


SCLA0PCFG

SCLA0 alternate function pin configuration register
address_offset : 0x86E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLA0PCFG SCLA0PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as SCLA0

0x02 : P01

P01 used as SCLA0

0x03 : P10

P10 used as SCLA0

0x04 : P11

P11 used as SCLA0

0x05 : P12

P12 used as SCLA0

0x06 : P13

P13 used as SCLA0

0x07 : P14

P14 used as SCLA0

0x08 : P15

P15 used as SCLA0

0x09 : P16

P16 used as SCLA0

0x0A : P17

P17 used as SCLA0

0x0B : P20

P20 used as SCLA0

0x0C : P21

P21 used as SCLA0

0x0D : P22

P22 used as SCLA0

0x0E : P23

P23 used as SCLA0

0x0F : P24

P24 used as SCLA0

0x10 : P25

P25 used as SCLA0

0x11 : P26

P26 used as SCLA0

0x12 : P27

P27 used as SCLA0

0x13 : P30

P30 used as SCLA0

0x14 : P31

P31 used as SCLA0

0x15 : P40

P40 used as SCLA0

0x16 : P41

P41 used as SCLA0

0x17 : P50

P50 used as SCLA0

0x18 : P51

P51 used as SCLA0

0x19 : P60

P60 used as SCLA0

0x1A : P61

P61 used as SCLA0

0x1B : P62

P62 used as SCLA0

0x1C : P63

P63 used as SCLA0

0x1D : P70

P70 used as SCLA0

0x1E : P71

P71 used as SCLA0

0x1F : P72

P72 used as SCLA0

0x20 : P73

P73 used as SCLA0

0x21 : P74

P74 used as SCLA0

0x22 : P75

P75 used as SCLA0

0x23 : P120

P120 used as SCLA0

0x24 : P121

P121 used as SCLA0

0x25 : P122

P122 used as SCLA0

0x26 : P123

P123 used as SCLA0

0x27 : P124

P124 used as SCLA0

0x28 : P130

P130 used as SCLA0

0x29 : P136

P136 used as SCLA0

0x2A : P137

P137 used as SCLA0

0x2B : P140

P140 used as SCLA0

0x2C : P146

P146 used as SCLA0

0x2D : P147

P147 used as SCLA0

End of enumeration elements list.


RXD1PCFG

RXD1 alternate function pin configuration register
address_offset : 0x86F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD1PCFG RXD1PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFG

CFG :
bits : 0 - 5 (6 bit)

Enumeration:

0x01 : P00

P00 used as RXD1

0x02 : P01

P01 used as RXD1

0x03 : P10

P10 used as RXD1

0x04 : P11

P11 used as RXD1

0x05 : P12

P12 used as RXD1

0x06 : P13

P13 used as RXD1

0x07 : P14

P14 used as RXD1

0x08 : P15

P15 used as RXD1

0x09 : P16

P16 used as RXD1

0x0A : P17

P17 used as RXD1

0x0B : P20

P20 used as RXD1

0x0C : P21

P21 used as RXD1

0x0D : P22

P22 used as RXD1

0x0E : P23

P23 used as RXD1

0x0F : P24

P24 used as RXD1

0x10 : P25

P25 used as RXD1

0x11 : P26

P26 used as RXD1

0x12 : P27

P27 used as RXD1

0x13 : P30

P30 used as RXD1

0x14 : P31

P31 used as RXD1

0x15 : P40

P40 used as RXD1

0x16 : P41

P41 used as RXD1

0x17 : P50

P50 used as RXD1

0x18 : P51

P51 used as RXD1

0x19 : P60

P60 used as RXD1

0x1A : P61

P61 used as RXD1

0x1B : P62

P62 used as RXD1

0x1C : P63

P63 used as RXD1

0x1D : P70

P70 used as RXD1

0x1E : P71

P71 used as RXD1

0x1F : P72

P72 used as RXD1

0x20 : P73

P73 used as RXD1

0x21 : P74

P74 used as RXD1

0x22 : P75

P75 used as RXD1

0x23 : P120

P120 used as RXD1

0x24 : P121

P121 used as RXD1

0x25 : P122

P122 used as RXD1

0x26 : P123

P123 used as RXD1

0x27 : P124

P124 used as RXD1

0x28 : P130

P130 used as RXD1

0x29 : P136

P136 used as RXD1

0x2A : P137

P137 used as RXD1

0x2B : P140

P140 used as RXD1

0x2C : P146

P146 used as RXD1

0x2D : P147

P147 used as RXD1

End of enumeration elements list.


SDA10PCFG

SDA10 alternate function pin configuration register
address_offset : 0x86F Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : RXD1PCFG
reset_Mask : 0x0

SDA10PCFG SDA10PCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDI10PCFG

SDI10 alternate function pin configuration register
address_offset : 0x86F Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : RXD1PCFG
reset_Mask : 0x0

SDI10PCFG SDI10PCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PMS

Port mode select register
address_offset : 0x87B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMS PMS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SPIPCFG

SPI alternate function pins configuration register
address_offset : 0x87E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPIPCFG SPIPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

P12

Port register 12
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P12 P12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P120 P121 P122 P123 P124

P120 : P12%s input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P121 : P12%s input/output data register
bits : 1 - 1 (1 bit)
access : read-write

P122 : P12%s input/output data register
bits : 2 - 2 (1 bit)
access : read-write

P123 : P12%s input/output data register
bits : 3 - 3 (1 bit)
access : read-write

P124 : P12%s input/output data register
bits : 4 - 4 (1 bit)
access : read-write


P13

Port register 13
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P13 P13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P130 P136 P137

P130 : P130 input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P136 : P13%s input/output data register
bits : 6 - 12 (7 bit)
access : read-write

P137 : P13%s input/output data register
bits : 7 - 13 (7 bit)
access : read-write


P14

Port register 14
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P14 P14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P140 P146 P147

P140 : P140 input/output data register
bits : 0 - 0 (1 bit)
access : read-write

P146 : P14%s input/output data register
bits : 6 - 12 (7 bit)
access : read-write

P147 : P14%s input/output data register
bits : 7 - 13 (7 bit)
access : read-write



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