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DTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

DTCEN0

DTCEN1

DTCEN2

DTCEN3

DTCEN4

DTCBAR


DTCEN0

DTC activation enable register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCEN0 DTCEN0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTCEN00 DTCEN01 DTCEN02 DTCEN03 DTCEN04 DTCEN05 DTCEN06 DTCEN07

DTCEN00 : DTC activation enable 0%s
bits : 0 - 0 (1 bit)
access : read-write

DTCEN01 : DTC activation enable 0%s
bits : 1 - 1 (1 bit)
access : read-write

DTCEN02 : DTC activation enable 0%s
bits : 2 - 2 (1 bit)
access : read-write

DTCEN03 : DTC activation enable 0%s
bits : 3 - 3 (1 bit)
access : read-write

DTCEN04 : DTC activation enable 0%s
bits : 4 - 4 (1 bit)
access : read-write

DTCEN05 : DTC activation enable 0%s
bits : 5 - 5 (1 bit)
access : read-write

DTCEN06 : DTC activation enable 0%s
bits : 6 - 6 (1 bit)
access : read-write

DTCEN07 : DTC activation enable 0%s
bits : 7 - 7 (1 bit)
access : read-write


DTCEN1

DTC activation enable register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCEN1 DTCEN1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTCEN10 DTCEN11 DTCEN12 DTCEN13 DTCEN14 DTCEN15 DTCEN16 DTCEN17

DTCEN10 : DTC activation enable 1%s
bits : 0 - 0 (1 bit)
access : read-write

DTCEN11 : DTC activation enable 1%s
bits : 1 - 1 (1 bit)
access : read-write

DTCEN12 : DTC activation enable 1%s
bits : 2 - 2 (1 bit)
access : read-write

DTCEN13 : DTC activation enable 1%s
bits : 3 - 3 (1 bit)
access : read-write

DTCEN14 : DTC activation enable 1%s
bits : 4 - 4 (1 bit)
access : read-write

DTCEN15 : DTC activation enable 1%s
bits : 5 - 5 (1 bit)
access : read-write

DTCEN16 : DTC activation enable 1%s
bits : 6 - 6 (1 bit)
access : read-write

DTCEN17 : DTC activation enable 1%s
bits : 7 - 7 (1 bit)
access : read-write


DTCEN2

DTC activation enable register 2
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCEN2 DTCEN2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTCEN20 DTCEN21 DTCEN22 DTCEN23 DTCEN24 DTCEN25 DTCEN26 DTCEN27

DTCEN20 : DTC activation enable 2%s
bits : 0 - 0 (1 bit)
access : read-write

DTCEN21 : DTC activation enable 2%s
bits : 1 - 1 (1 bit)
access : read-write

DTCEN22 : DTC activation enable 2%s
bits : 2 - 2 (1 bit)
access : read-write

DTCEN23 : DTC activation enable 2%s
bits : 3 - 3 (1 bit)
access : read-write

DTCEN24 : DTC activation enable 2%s
bits : 4 - 4 (1 bit)
access : read-write

DTCEN25 : DTC activation enable 2%s
bits : 5 - 5 (1 bit)
access : read-write

DTCEN26 : DTC activation enable 2%s
bits : 6 - 6 (1 bit)
access : read-write

DTCEN27 : DTC activation enable 2%s
bits : 7 - 7 (1 bit)
access : read-write


DTCEN3

DTC activation enable register 3
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCEN3 DTCEN3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTCEN30 DTCEN31 DTCEN32 DTCEN33 DTCEN34 DTCEN35 DTCEN36 DTCEN37

DTCEN30 : DTC activation enable 3%s
bits : 0 - 0 (1 bit)
access : read-write

DTCEN31 : DTC activation enable 3%s
bits : 1 - 1 (1 bit)
access : read-write

DTCEN32 : DTC activation enable 3%s
bits : 2 - 2 (1 bit)
access : read-write

DTCEN33 : DTC activation enable 3%s
bits : 3 - 3 (1 bit)
access : read-write

DTCEN34 : DTC activation enable 3%s
bits : 4 - 4 (1 bit)
access : read-write

DTCEN35 : DTC activation enable 3%s
bits : 5 - 5 (1 bit)
access : read-write

DTCEN36 : DTC activation enable 3%s
bits : 6 - 6 (1 bit)
access : read-write

DTCEN37 : DTC activation enable 3%s
bits : 7 - 7 (1 bit)
access : read-write


DTCEN4

DTC activation enable register 4
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCEN4 DTCEN4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTCEN40 DTCEN41 DTCEN42 DTCEN43 DTCEN44 DTCEN45 DTCEN46 DTCEN47

DTCEN40 : DTC activation enable 4%s
bits : 0 - 0 (1 bit)
access : read-write

DTCEN41 : DTC activation enable 4%s
bits : 1 - 1 (1 bit)
access : read-write

DTCEN42 : DTC activation enable 4%s
bits : 2 - 2 (1 bit)
access : read-write

DTCEN43 : DTC activation enable 4%s
bits : 3 - 3 (1 bit)
access : read-write

DTCEN44 : DTC activation enable 4%s
bits : 4 - 4 (1 bit)
access : read-write

DTCEN45 : DTC activation enable 4%s
bits : 5 - 5 (1 bit)
access : read-write

DTCEN46 : DTC activation enable 4%s
bits : 6 - 6 (1 bit)
access : read-write

DTCEN47 : DTC activation enable 4%s
bits : 7 - 7 (1 bit)
access : read-write


DTCBAR

DTC base address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCBAR DTCBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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