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EPWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

EPWMSRC

EPWMSTR

EPWMSTC

EPWMCTL

EPWMSTL


EPWMSRC

Input source select register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPWMSRC EPWMSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC00 SRC01 SRC02 SRC03 SRC04 SRC05 SRC06 SRC07

SRC00 : Selsect the source clock of EPWM0%s
bits : 0 - 0 (1 bit)

SRC01 : Selsect the source clock of EPWM0%s
bits : 1 - 1 (1 bit)

SRC02 : Selsect the source clock of EPWM0%s
bits : 2 - 2 (1 bit)

SRC03 : Selsect the source clock of EPWM0%s
bits : 3 - 3 (1 bit)

SRC04 : Selsect the source clock of EPWM0%s
bits : 4 - 4 (1 bit)

SRC05 : Selsect the source clock of EPWM0%s
bits : 5 - 5 (1 bit)

SRC06 : Selsect the source clock of EPWM0%s
bits : 6 - 6 (1 bit)

SRC07 : Selsect the source clock of EPWM0%s
bits : 7 - 7 (1 bit)


EPWMSTR

Status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPWMSTR EPWMSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HZCLR SHTFLG

HZCLR : software release cutoff register
bits : 0 - 0 (1 bit)

SHTFLG : cutoff status register
bits : 1 - 2 (2 bit)


EPWMSTC

EPWMO0n cutoff control register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPWMSTC EPWMSTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC_SEL0 SC_SEL1 IN_EG HS_SEL REL_SEL

SC_SEL0 : Cutoff source selection
bits : 0 - 0 (1 bit)

SC_SEL1 : Cutoff source selection
bits : 1 - 1 (1 bit)

IN_EG : Output forced cutoff source edge/output forced cutoff release edge selection
bits : 2 - 4 (3 bit)

HS_SEL : Output forced cutoff release mode selection
bits : 3 - 6 (4 bit)

REL_SEL : Cutoff release timing select register
bits : 4 - 8 (5 bit)


EPWMCTL

EPWMO0n output control register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPWMCTL EPWMCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OE00 OE01 OE02 OE03 OE04 OE05 OE06 OE07 IE00 IE01 IE02 IE03 IE04 IE05 IE06 IE07

OE00 : EPWM0%s output enable register
bits : 0 - 0 (1 bit)

OE01 : EPWM0%s output enable register
bits : 1 - 1 (1 bit)

OE02 : EPWM0%s output enable register
bits : 2 - 2 (1 bit)

OE03 : EPWM0%s output enable register
bits : 3 - 3 (1 bit)

OE04 : EPWM0%s output enable register
bits : 4 - 4 (1 bit)

OE05 : EPWM0%s output enable register
bits : 5 - 5 (1 bit)

OE06 : EPWM0%s output enable register
bits : 6 - 6 (1 bit)

OE07 : EPWM0%s output enable register
bits : 7 - 7 (1 bit)

IE00 : EPWM0%s output inverted enable register
bits : 8 - 16 (9 bit)

IE01 : EPWM0%s output inverted enable register
bits : 9 - 17 (9 bit)

IE02 : EPWM0%s output inverted enable register
bits : 10 - 18 (9 bit)

IE03 : EPWM0%s output inverted enable register
bits : 11 - 19 (9 bit)

IE04 : EPWM0%s output inverted enable register
bits : 12 - 20 (9 bit)

IE05 : EPWM0%s output inverted enable register
bits : 13 - 21 (9 bit)

IE06 : EPWM0%s output inverted enable register
bits : 14 - 22 (9 bit)

IE07 : EPWM0%s output inverted enable register
bits : 15 - 23 (9 bit)


EPWMSTL

EPWMO0n cutoff output level register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPWMSTL EPWMSTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO00 IO01 IO10 IO11 IO20 IO21 IO30 IO31 IO40 IO41 IO50 IO51 IO60 IO61 IO70 IO71

IO00 : EPWM00 output enable register
bits : 0 - 0 (1 bit)

IO01 : EPWM00 output enable register
bits : 1 - 1 (1 bit)

IO10 : EPWM01 output enable register
bits : 2 - 4 (3 bit)

IO11 : EPWM01 output enable register
bits : 3 - 5 (3 bit)

IO20 : EPWM02 output enable register
bits : 4 - 8 (5 bit)

IO21 : EPWM02 output enable register
bits : 5 - 9 (5 bit)

IO30 : EPWM03 output enable register
bits : 6 - 12 (7 bit)

IO31 : EPWM03 output enable register
bits : 7 - 13 (7 bit)

IO40 : EPWM04 output enable register
bits : 8 - 16 (9 bit)

IO41 : EPWM04 output enable register
bits : 9 - 17 (9 bit)

IO50 : EPWM05 output enable register
bits : 10 - 20 (11 bit)

IO51 : EPWM05 output enable register
bits : 11 - 21 (11 bit)

IO60 : EPWM06 output enable register
bits : 12 - 24 (13 bit)

IO61 : EPWM06 output enable register
bits : 13 - 25 (13 bit)

IO70 : EPWM07 output enable register
bits : 14 - 28 (15 bit)

IO71 : EPWM07 output enable register
bits : 15 - 29 (15 bit)



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