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DMAVEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C0 byte (0x0)
mem_usage : registers
protection :

Registers

VEC0

DMACR

VEC1

VEC16

VEC17

VEC18

VEC19

VEC20

VEC21

VEC22

VEC23

VEC24

VEC25

VEC26

VEC27

VEC28

VEC29

VEC30

VEC31

VEC2

DMBLS

VEC3

VEC4

DMACT

VEC5

VEC6

DMRLD

VEC7

VEC8

DMSAR

VEC9

VEC10

VEC11

VEC12

DMDAR

VEC13

VEC14

VEC15


VEC0

DMA vector area
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC0 VEC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMACR

DMA Control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACR DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE RPTSEL SAMOD DAMOD CHNE RPTINT SZ

MODE : Transfer mode selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Normal

Normal mode

1 : Repeat

Repeat mode

End of enumeration elements list.

RPTSEL : Repeat area selection
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : destination

Transfer destination is the repeat area

1 : source

Transfer source is the repeat area

End of enumeration elements list.

SAMOD : Source address control
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : Fixed

Fixed

1 : Incremented

Incremented

End of enumeration elements list.

DAMOD : Destination address control
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Fixed

Fixed

1 : Incremented

Incremented

End of enumeration elements list.

CHNE : Enabling/disabling chain transfers
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : disable

Chain transfers disabled

1 : enable

Chain transfers enabled

End of enumeration elements list.

RPTINT : Enabling/disabling repeat mode interrupts
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : disable

Interrupt generation disabled

1 : enable

Interrupt generation enabled

End of enumeration elements list.

SZ : Transfer Data size selection
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

0 : BYTE

8 bits

1 : HALF

16 bits

2 : WORD

32 bits

End of enumeration elements list.


VEC1

DMA vector area
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC1 VEC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC16

DMA vector area
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC16 VEC16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC17

DMA vector area
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC17 VEC17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC18

DMA vector area
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC18 VEC18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC19

DMA vector area
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC19 VEC19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC20

DMA vector area
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC20 VEC20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC21

DMA vector area
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC21 VEC21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC22

DMA vector area
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC22 VEC22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC23

DMA vector area
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC23 VEC23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC24

DMA vector area
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC24 VEC24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC25

DMA vector area
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC25 VEC25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC26

DMA vector area
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC26 VEC26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC27

DMA vector area
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC27 VEC27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC28

DMA vector area
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC28 VEC28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC29

DMA vector area
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC29 VEC29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC30

DMA vector area
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC30 VEC30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC31

DMA vector area
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC31 VEC31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC2

DMA vector area
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC2 VEC2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMBLS

DMA Block Size register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMBLS DMBLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VEC3

DMA vector area
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC3 VEC3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC4

DMA vector area
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC4 VEC4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMACT

DMA Transfer Count register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACT DMACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VEC5

DMA vector area
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC5 VEC5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC6

DMA vector area
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC6 VEC6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMRLD

DMA Transfer Count Reload register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMRLD DMRLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VEC7

DMA vector area
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC7 VEC7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC8

DMA vector area
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC8 VEC8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMSAR

DMA Source Address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSAR DMSAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VEC9

DMA vector area
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC9 VEC9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC10

DMA vector area
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC10 VEC10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC11

DMA vector area
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC11 VEC11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC12

DMA vector area
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC12 VEC12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMDAR

DMA Destination Address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMDAR DMDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VEC13

DMA vector area
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC13 VEC13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC14

DMA vector area
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC14 VEC14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

VEC15

DMA vector area
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VEC15 VEC15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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