\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

CMC

CSC

HIOTRM

HOCODIV

OSTC

PER0

OSMC

OSTS

CKC

PER1


CMC

Clock operaton Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMC CMC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPH AMPHS OSCSELS EXCLKS OSCSEL EXCLK

AMPH : Control of X1 clock oscillation frequency
bits : 0 - 0 (1 bit)
access : read-write

AMPHS : Control of XT1 clock oscillation frequency
bits : 1 - 3 (3 bit)
access : read-write

OSCSELS : Sub OSC Select
bits : 4 - 8 (5 bit)
access : read-write

EXCLKS : External Clock input mode
bits : 5 - 10 (6 bit)
access : read-write

OSCSEL : Main OSC Select
bits : 6 - 12 (7 bit)
access : read-write

EXCLK : External Clock input mode
bits : 7 - 14 (8 bit)
access : read-write


CSC

Clock operation Status Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSC CSC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HIOSTOP XTSTOP MSTOP

HIOSTOP : High-speed on-chip oscillator clock operation control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : START

High-speed on-chip oscillator operating

1 : STOP

High-speed on-chip oscillator stopped

End of enumeration elements list.

XTSTOP : Subsystem clock operation control
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : START

XT1 oscillator operating or External clock from EXCLKS pin is valid

1 : STOP

XT1 oscillator stop or External clock from EXCLKS pin is invalid

End of enumeration elements list.

MSTOP : High-speed system clock operation control
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : START

X1 oscillator operating or External clock from EXCLK pin is valid

1 : STOP

X1 oscillator stop or External clock from EXCLK pin is invalid

End of enumeration elements list.


HIOTRM

High-speed on-chip oscillator trimming register
address_offset : 0x1800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIOTRM HIOTRM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

HOCODIV

High-speed on-chip oscillator frequency select register
address_offset : 0x1820 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCODIV HOCODIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

OSTC

Oscillation stabilization time counter status
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSTC OSTC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PER0

Peripheral enable register 0
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER0 PER0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TAU0EN SAU0EN SAU1EN IICA0EN ADCEN IRDAEN RTCEN

TAU0EN : Control of the TAU0 input clock
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SAU0EN : Control of the SAU0 input clock
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SAU1EN : Control of the SAU1 input clock
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

IICA0EN : Control of the IICA0 input clock
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

ADCEN : Control of the ADC input clock
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

IRDAEN : Control of the IRDA input clock
bits : 6 - 12 (7 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

RTCEN : Control of the RTC input clock
bits : 7 - 14 (8 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.


OSMC

Subsystem clock supply mode control register
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSMC OSMC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WUTMMCK0 RTCLPC

WUTMMCK0 : Selection of operation clock for RTC, IT and timer A
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : fSUB

The subsystem clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. The low-speed on-chip oscillator cannot be selected as the count source for timer A.

1 : fIL

The low-speed on-chip oscillator clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. Either the low-speed on-chip oscillator or the subsystem clock can be selected as the count source for timer A.

End of enumeration elements list.

RTCLPC : Low Power control in Standby mode
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Enable

Enables supply of subsystem clock to peripheral function

1 : Disable

Stops supply of subsystem clock to peripheral functions other than real-time clock and 15-bit interval timer.

End of enumeration elements list.


OSTS

Oscillation stabilization time select register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTS OSTS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CKC

System clock control register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKC CKC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MCM0 MCS CSS CLS

MCM0 : Main system clock (fMAIN) operation control
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : fIH

Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)

1 : fMX

Select the high-speed system clock (fMX) as the main system clock (fMAIN)

End of enumeration elements list.

MCS : Status of Main system clock (fMAIN)
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : fIH

High-speed on-chip oscillator clock (fIH)

1 : fMX

High-speed system clock (fMX)

End of enumeration elements list.

CSS : Selection of CPU/peripheral hardware clock (fCLK)
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : fMAIN

Main system clock (fMAIN)

1 : fSUB

Subsystem clock (fSUB)

End of enumeration elements list.

CLS : Status of CPU/peripheral hardware clock (fCLK)
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : fMAIN

Main system clock (fMAIN)

1 : fSUB

Subsystem clock (fSUB)

End of enumeration elements list.


PER1

Peripheral enable register 1
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER1 PER1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRJ0EN TRXEN PWMOPEN DTCEN TRD0EN PGACMPEN TRGEN DACEN

TRJ0EN : Control of the TRJ0 input clock
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

TRXEN : Control of the TRX input clock
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

PWMOPEN : Control of the PWMOP input clock
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

DTCEN : Control of the DTC input clock
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

TRD0EN : Control of the TRD0 input clock
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

PGACMPEN : Control of the PGACMP input clock
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

TRGEN : Control of the TRG input clock
bits : 6 - 12 (7 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

DACEN : Control of the DAC input clock
bits : 7 - 14 (8 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.