\n

TAU0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

TCR00

TMR00

TMR01

TMR02

TMR03

TDR00

TDR01

TDR01L

TDR01H

TDR02

TDR03

TDR03L

TDR03H

TCR01

TSR00

TSR01

TSR02

TSR03

TE0

TS0

TT0

TPS0

TO0

TOE0

TOL0

TOM0

TCR02

TCR03


TCR00

Timer count register 0%s
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR00 TCR00 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMR00

Timer mode register mn
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR00 TMR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD00 CIS00 STS00 CCS00 CKS00

MD00 : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS00 : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS00 : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

CCS00 : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS00 : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TMR01

Timer mode register mn
address_offset : 0x12 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR01 TMR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD01 CIS01 STS01 SPLIT01 CCS01 CKS01

MD01 : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS01 : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS01 : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

SPLIT01 : Selection of 8 or 16-bit timer operation for channels 1 and 3
bits : 11 - 22 (12 bit)
access : read-write

CCS01 : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS01 : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TMR02

Timer mode register mn
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR02 TMR02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD02 CIS02 STS02 MASTER02 CCS02 CKS02

MD02 : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS02 : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS02 : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

MASTER02 : Selection between using channel n independently or simultaneously with another channel (as a slave or master)
bits : 11 - 22 (12 bit)
access : read-write

CCS02 : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS02 : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TMR03

Timer mode register mn
address_offset : 0x16 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR03 TMR03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD03 CIS03 STS03 SPLIT03 CCS03 CKS03

MD03 : Operation mode of channel n
bits : 0 - 3 (4 bit)
access : read-write

CIS03 : Selection of TImn pin input valid edge
bits : 6 - 13 (8 bit)
access : read-write

STS03 : Setting of start trigger or capture trigger of channel n
bits : 8 - 18 (11 bit)
access : read-write

SPLIT03 : Selection of 8 or 16-bit timer operation for channels 1 and 3
bits : 11 - 22 (12 bit)
access : read-write

CCS03 : Selection of count clock (fTCLK) of channel n
bits : 12 - 24 (13 bit)
access : read-write

CKS03 : Selection of operation clock (fMCK) of channel n
bits : 14 - 29 (16 bit)
access : read-write


TDR00

Timer data register 0%s
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR00 TDR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR01

Timer data register 0%s
address_offset : 0x19A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR01 TDR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR01L

Timer data lower register 01
address_offset : 0x19A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR01
reset_Mask : 0x0

TDR01L TDR01L read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR01H

Timer data higher register 01
address_offset : 0x19B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR01
reset_Mask : 0x0

TDR01H TDR01H read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR02

Timer data register 0%s
address_offset : 0x1E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR02 TDR02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR03

Timer data register 0%s
address_offset : 0x1E6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR03 TDR03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR03L

Timer data lower register 03
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR03
reset_Mask : 0x0

TDR03L TDR03L read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR03H

Timer data higher register 03
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : TDR03
reset_Mask : 0x0

TDR03H TDR03H read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TCR01

Timer count register 0%s
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR01 TCR01 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR00

Timer status register mn
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSR00 TSR00 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR01

Timer status register mn
address_offset : 0x22 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR01 TSR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR02

Timer status register mn
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR02 TSR02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSR03

Timer status register mn
address_offset : 0x26 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR03 TSR03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TE0

Timer channel enable status register m
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TE0 TE0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TE00 TE01 TE02 TE03 TEH01 TEH03

TE00 : Indicate operation status of channel 0
bits : 0 - 0 (1 bit)

TE01 : Indicate operation status of channel 1
bits : 1 - 2 (2 bit)

TE02 : Indicate operation status of channel 2
bits : 2 - 4 (3 bit)

TE03 : Indicate operation status of channel 3
bits : 3 - 6 (4 bit)

TEH01 : Indicate operation stauts of the higher 8-bit timer
bits : 9 - 18 (10 bit)

TEH03 : Indicate operation stauts of the higher 8-bit timer
bits : 11 - 22 (12 bit)


TS0

Timer channel start register 0
address_offset : 0x32 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TS0 TS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS00 TS01 TS02 TS03 TSH01 TSH03

TS00 : Operation enable (start) trigger of channel 0
bits : 0 - 0 (1 bit)

TS01 : Operation enable (start) trigger of channel 1
bits : 1 - 2 (2 bit)

TS02 : Operation enable (start) trigger of channel 2
bits : 2 - 4 (3 bit)

TS03 : Operation enable (start) trigger of channel 3
bits : 3 - 6 (4 bit)

TSH01 : Operation enable (start) of the higher 8-bit timer
bits : 9 - 18 (10 bit)

TSH03 : Operation enable (start) of the higher 8-bit timer
bits : 11 - 22 (12 bit)


TT0

Timer channel stop register 0
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TT0 TT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TT00 TT01 TT02 TT03 TTH01 TTH03

TT00 : Operation stop trigger of channel 0
bits : 0 - 0 (1 bit)

TT01 : Operation stop trigger of channel 1
bits : 1 - 2 (2 bit)

TT02 : Operation stop trigger of channel 2
bits : 2 - 4 (3 bit)

TT03 : Operation stop trigger of channel 3
bits : 3 - 6 (4 bit)

TTH01 : Trigger to stop operation of the higher 8-bit timer
bits : 9 - 18 (10 bit)

TTH03 : Trigger to stop operation of the higher 8-bit timer
bits : 11 - 22 (12 bit)


TPS0

Timer clock select register 0
address_offset : 0x36 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPS0 TPS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS00 PRS01 PRS02 PRS03

PRS00 : Prescaler 0
bits : 0 - 3 (4 bit)

PRS01 : Prescaler 1
bits : 4 - 11 (8 bit)

PRS02 : Prescaler 2
bits : 8 - 17 (10 bit)

PRS03 : Prescaler 3
bits : 12 - 25 (14 bit)


TO0

Timer output register 0
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TO0 TO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO00 TO01 TO02 TO03

TO00 : Timer output of channel 0
bits : 0 - 0 (1 bit)

TO01 : Timer output of channel 1
bits : 1 - 2 (2 bit)

TO02 : Timer output of channel 2
bits : 2 - 4 (3 bit)

TO03 : Timer output of channel 3
bits : 3 - 6 (4 bit)


TOE0

Timer output enable register 0
address_offset : 0x3A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOE0 TOE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOE00 TOE01 TOE02 TOE03

TOE00 : Timer output enable of channel 0
bits : 0 - 0 (1 bit)

TOE01 : Timer output enable of channel 1
bits : 1 - 2 (2 bit)

TOE02 : Timer output enable of channel 2
bits : 2 - 4 (3 bit)

TOE03 : Timer output enable of channel 3
bits : 3 - 6 (4 bit)


TOL0

Timer output level register 0
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOL0 TOL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOL01 TOL02 TOL03

TOL01 : Control of timer output level of channel 1
bits : 1 - 2 (2 bit)

TOL02 : Control of timer output level of channel 2
bits : 2 - 4 (3 bit)

TOL03 : Control of timer output level of channel 3
bits : 3 - 6 (4 bit)


TOM0

Timer output mode register 0
address_offset : 0x3E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOM0 TOM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOM01 TOM02 TOM03

TOM01 : Control of timer output mode of channel 1
bits : 1 - 2 (2 bit)

TOM02 : Control of timer output mode of channel 2
bits : 2 - 4 (3 bit)

TOM03 : Control of timer output mode of channel 3
bits : 3 - 6 (4 bit)


TCR02

Timer count register 0%s
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR02 TCR02 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCR03

Timer count register 0%s
address_offset : 0x6 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCR03 TCR03 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.